公开(公告)号：US20160042488A1

公开(公告)日：2016-02-11

申请号：US14820221

申请日：2015-08-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Jonathan Lawrence Campbell ,  Mitchell H. Singer ,  Yuping Shen ,  Yue Zhuo

IPC: G06T1/20 ,  G06T1/60 ,  G06F17/30

CPC classification number: G06T1/20 ,  G06F17/30044 ,  G06T1/60 ,  G09G5/363 ,  G09G2340/0435 ,  G09G2360/06

Abstract: A frame pacing method, computer program product, and computing system are provided for graphics processing.

Abstract translation: 提供了一种帧起搏方法，计算机程序产品和计算系统，用于图形处理。

公开(公告)号：US20220058767A1

公开(公告)日：2022-02-24

申请号：US17519992

申请日：2021-11-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Hans Fernlund ,  Mitchell H. Singer ,  Manu Rastogi

IPC: G06T1/20 ,  G06F9/30 ,  G09G5/395 ,  G09G5/36 ,  G06T1/60

Abstract: Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer.

公开(公告)号：US11170462B1

公开(公告)日：2021-11-09

申请号：US17032309

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Hans Fernlund ,  Mitchell H. Singer ,  Manu Rastogi

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/30 ,  G09G5/395 ,  G09G5/36

Abstract: Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer.

公开(公告)号：US09679345B2

公开(公告)日：2017-06-13

申请号：US14820221

申请日：2015-08-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Jonathan Lawrence Campbell ,  Mitchell H. Singer ,  Yuping Shen ,  Yue Zhuo

IPC: G06T1/20 ,  G06F17/30 ,  G09G5/36

CPC classification number: G06T1/20 ,  G06F17/30044 ,  G06T1/60 ,  G09G5/363 ,  G09G2340/0435 ,  G09G2360/06

Abstract: A frame pacing method, computer program product, and computing system are provided for graphics processing. A method and system for frame pacing adds a delay which evenly spaces out the display of the subsequent frames, and a measurement mechanism which measures and adjusts the delay as application workload changes in an evenly spaced manner.