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公开(公告)号：US20240330046A1
公开(公告)日：2024-10-03
申请号：US18374837
申请日：2023-09-29
CPC分类号： G06F9/4881 , G06F9/5038 , G06F2209/5021
摘要： A processing device includes a hardware scheduler, an unmapped queue unit, and command processor, and a plurality of compute units. Responsive to a queue doorbell being an unmapped queue doorbell, the unmapped queue unit is configured to transmit a signal to the hardware scheduler indicating work has been placed into a queue currently unmapped to a hardware queue of the processing device. The hardware scheduler is configured to map the queue to a hardware queue of a plurality of hardware queues at the processing device in response to the signal. The command processor is configured to dispatch the work associated with the mapped queue to one or more compute units of the plurality of compute units.
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公开(公告)号：US12056787B2
公开(公告)日：2024-08-06
申请号：US17564049
申请日：2021-12-28
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： Methods and systems are disclosed for inline suspension of an accelerated processing unit (APU). Techniques include receiving a packet, including a mode of operation and commands to be executed by the APU; suspending execution of commands received in previous packets when the mode of operation is a suspension initiation mode; and executing, by the APU, the commands in the received packet. The execution of the suspended commands is restored when the mode of operation in a subsequently received packet is a suspension conclusion mode.
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公开(公告)号：US11900123B2
公开(公告)日：2024-02-13
申请号：US16713432
申请日：2019-12-13
CPC分类号： G06F9/3869 , G06F9/3836 , G06F15/80 , G06T1/20
摘要： A system includes a processing unit such as a GPU that itself includes a command processor configured to receive instructions for execution from a software application. A processor pipeline coupled to the processing unit includes a set of parallel processing units for executing the instructions in sets. A set manager is coupled to one or more of the processor pipeline and the command processor. The set manager includes at least one table for storing a set start time, a set end time, and a set execution time. The set manager determines an execution time for one or more sets of instructions of a first window of sets of instructions submitted to the processor pipeline. Based on the execution time of the one or more sets of instructions, a set limit is determined and applied to one or more sets of instructions of a second window subsequent to the first window.
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公开(公告)号：US11809558B2
公开(公告)日：2023-11-07
申请号：US17032969
申请日：2020-09-25
CPC分类号： G06F21/566 , G06F9/30076 , G06F9/3802 , G06F21/54 , G06F21/567 , H04L69/22
摘要： A method of packet attribute confirmation includes receiving, at a command processor of a parallel processor, a command packet including a received packet attribute, such as a packet size, of the command packet. The command processor compares the received packet attribute of the command packet relative to an expected packet attribute of the command packet. The command processor passes one or more commands to a prefetch parser such that a summed total size of the one or more commands is equal to the received packet size of the command packet. The command processor passes, based at least on determining a match between the received packet size and the expected packet size, the received command packet to the prefetch parser. Otherwise, the command processor passes, based at least on determining a mismatch between the received packet size and the expected packet size, one or more no-operation instructions to the prefetch parser.
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公开(公告)号：US20230206379A1
公开(公告)日：2023-06-29
申请号：US17564049
申请日：2021-12-28
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： Methods and systems are disclosed for inline suspension of an accelerated processing unit (APU). Techniques include receiving a packet, including a mode of operation and commands to be executed by the APU; suspending execution of commands received in previous packets when the mode of operation is a suspension initiation mode; and executing, by the APU, the commands in the received packet. The execution of the suspended commands is restored when the mode of operation in a subsequently received packet is a suspension conclusion mode.
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公开(公告)号：US20220058767A1
公开(公告)日：2022-02-24
申请号：US17519992
申请日：2021-11-05
发明人： Hans Fernlund , Mitchell H. Singer , Manu Rastogi
摘要： Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer.
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公开(公告)号：US20240192994A1
公开(公告)日：2024-06-13
申请号：US18127395
申请日：2023-03-28
发明人： Alexander Fuad Ashkar , Michael Mantor , Rex Eldon McCrary , Yi Luo , Manu Rastogi , James Robert Klobcar
CPC分类号： G06F9/5027 , G06F9/4881
摘要： Techniques for implementing accelerated draw indirect fetching are disclosed. A fetch accelerator enables streamlined data fetching by looping internally and filling a draw queue for a micro engine. By using a dedicated fetch accelerator rather than processing data fetches separately and individually using a conventional processor, significant processing overhead is eliminated and computational latency is reduced. Additionally, different types of aligned or unaligned data structures are usable with equivalent or nearly equivalent performance.
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公开(公告)号：US20240087078A1
公开(公告)日：2024-03-14
申请号：US18337322
申请日：2023-06-19
CPC分类号： G06T1/60 , G06T1/20 , G06T15/005 , G06T15/40
摘要： Methods, devices, and systems for rendering primitives in a frame. During a visibility pass, state packets are processed to determine a register state, and the register state is stored in a memory device. During a rendering pass, the state packets are discarded and the register state is read from the memory device. In some implementations, a graphics pipeline is configured during the visibility pass based on the register state determined by processing the state packets, and the graphics pipeline is configured during the rendering pass based on the register state read from the memory device. In some implementations, replay control packets, draw packets, and the state packets, from a packet stream, are processed during the visibility pass; the draw packets are modified based on visibility information determined during the visibility pass; and the replay control packets and draw packets are processed, during the rendering pass.
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公开(公告)号：US11170462B1
公开(公告)日：2021-11-09
申请号：US17032309
申请日：2020-09-25
发明人： Hans Fernlund , Mitchell H. Singer , Manu Rastogi
摘要： Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer.
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