公开(公告)号：US11170462B1

公开(公告)日：2021-11-09

申请号：US17032309

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Hans Fernlund ,  Mitchell H. Singer ,  Manu Rastogi

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/30 ,  G09G5/395 ,  G09G5/36

Abstract: Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer.

公开(公告)号：US20220058767A1

公开(公告)日：2022-02-24

申请号：US17519992

申请日：2021-11-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Hans Fernlund ,  Mitchell H. Singer ,  Manu Rastogi

IPC: G06T1/20 ,  G06F9/30 ,  G09G5/395 ,  G09G5/36 ,  G06T1/60

Abstract: Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer.

公开(公告)号：US11243799B2

公开(公告)日：2022-02-08

申请号：US16556521

申请日：2019-08-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexander Fuad Ashkar ,  Hans Fernlund

IPC: G06F9/455 ,  G06F9/38

Abstract: An apparatus includes a plurality of virtual machines, a hypervisor coupled to the plurality of virtual machines, and a graphical processing unit (GPU) coupled to the hypervisor. The plurality of virtual machines are allocated a plurality of time slices. The hypervisor initiates a world switch to a first virtual machine of the plurality of virtual machines. The GPU makes a determination as to whether to adjust the time slice associated with the first virtual machine based on an assessment of time slice adjustment parameters related to an execution time of at least one of the plurality of virtual machines.