公开(公告)号：US11023241B2

公开(公告)日：2021-06-01

申请号：US16106515

申请日：2018-08-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrej Kocev ,  Jay Fleischman ,  Kai Troester ,  Johnny C. Chu ,  Tim J. Wilkens ,  Neil Marketkar ,  Michael W. Long

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems and methods selectively bypass address-generation hardware in processor instruction pipelines. In an embodiment, a processor includes an address-generation stage and an address-generation-bypass-determination unit (ABDU). The ABDU receives a load/store instruction. If an effective address for the load/store instruction is not known at the ABDU, the ABDU routes the load/store instruction via the address-generation stage of the processor. If, however, the effective address of the load/store instruction is known at the ABDU, the ABDU routes the load/store instruction to bypass the address-generation stage of the processor.

公开(公告)号：US20210096920A1

公开(公告)日：2021-04-01

申请号：US16585424

申请日：2019-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Kai Troester ,  Neil Marketkar ,  Matthew T. Sobel ,  Srinivas Keshav

IPC: G06F9/50 ,  G06F9/48

Abstract: An approach is provided for allocating a shared resource to threads in a multi-threaded microprocessor based upon the usefulness of the shared resource to each of the threads. The usefulness of a shared resource to a thread is determined based upon the number of entries in the shared resource that are allocated to the thread and the number of active entries that the thread has in the shared resource. Threads that are allocated a large number of entries in the shared resource and have a small number of active entries in the shared resource, indicative of a low level of parallelism, can operate efficiently with fewer entries in the shared resource, and have their allocation limit in the shared resource reduced.

公开(公告)号：US11294724B2

公开(公告)日：2022-04-05

申请号：US16585424

申请日：2019-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Kai Troester ,  Neil Marketkar ,  Matthew T. Sobel ,  Srinivas Keshav

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48

Abstract: An approach is provided for allocating a shared resource to threads in a multi-threaded microprocessor based upon the usefulness of the shared resource to each of the threads. The usefulness of a shared resource to a thread is determined based upon the number of entries in the shared resource that are allocated to the thread and the number of active entries that the thread has in the shared resource. Threads that are allocated a large number of entries in the shared resource and have a small number of active entries in the shared resource, indicative of a low level of parallelism, can operate efficiently with fewer entries in the shared resource, and have their allocation limit in the shared resource reduced.