公开(公告)号：US09317250B2

公开(公告)日：2016-04-19

申请号：US13674220

申请日：2012-11-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Kelvin D. Goveas ,  Debjit Das Sarma ,  Scott A. Hilker ,  Hanbing Liu

IPC: G06F7/483 ,  G06F7/499 ,  G06F7/544

CPC classification number: G06F7/483 ,  G06F7/49936 ,  G06F7/5443

Abstract: The present application provides a method and apparatus for supporting denormal numbers in a floating point multiply-add unit (FMAC). One embodiment of the FMAC is configurable to add a product of first and second operands to a third operand. This embodiment of the FMAC is configurable to determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product. This embodiment of the FMAC is also configurable to cause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum.

Abstract translation: 本申请提供了一种用于支持浮点乘法单元（FMAC）中的反常数的方法和装置。 FMAC的一个实施例可配置为将第一和第二操作数的乘积添加到第三操作数。 FMAC的该实施例可配置为通过从乘积的乘积指数减去最小正态指数来确定乘积和第三操作数之和的最小指数偏移。 如果FMAC的这个实施例如果第三操作数的第三指数小于或等于乘积指数并且最小指数移位小于或等于，则可配置为使表示和的位移动移位最小指数移位 到总和的预测左移。