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1.发明授权公开(公告)号：US12135625B2
公开(公告)日：2024-11-05
申请号：US18089135
申请日：2022-12-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Vilas Sridharan , Hanbing Liu , Francisco L. Duran
Abstract: An exemplary system includes and/or represents an agent and a machine check architecture. In one example, the machine check architecture includes and/or represents at least one circuit configured to report errors via at least one reporting register. In this example, the machine check architecture also includes and/or represents at least one error-injection register configured to cause the circuit to inject at least one fabricated error report into the reporting register in response to a write operation performed by the agent on at least one bit of the error-injection register. Various other devices, systems, and methods are also disclosed.
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Patent Agency Ranking
2.发明公开公开(公告)号：US20240211362A1
公开(公告)日：2024-06-27
申请号：US18089135
申请日：2022-12-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Vilas Sridharan , Hanbing Liu , Francisco L. Duran
CPC classification number: G06F11/261 , G06F11/0784 , G06F11/0787
Abstract: An exemplary system includes and/or represents an agent and a machine check architecture. In one example, the machine check architecture includes and/or represents at least one circuit configured to report errors via at least one reporting register. In this example, the machine check architecture also includes and/or represents at least one error-injection register configured to cause the circuit to inject at least one fabricated error report into the reporting register in response to a write operation performed by the agent on at least one bit of the error-injection register. Various other devices, systems, and methods are also disclosed.
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公开(公告)号：US20190196839A1
公开(公告)日：2019-06-27
申请号：US15853169
申请日：2017-12-22
Applicant: Advanced Micro Devices, Inc.
CPC classification number: G06F9/3855 , G06F9/3005
Abstract: A system and method for increasing address generation operations per cycle is described. In particular, a unified address generation scheduler queue (AGSQ) is a single queue structure which is accessed by first and second pickers in a picking cycle. Picking collisions are avoided by assigning a first set of entries to the first picker and a second set of entries to the second picker. The unified AGSQ uses a shifting, collapsing queue structure to shift other micro-operations into issued entries, which in turn collapses the queue and re-balances the unified AGSQ. A second level and delayed picker picks a third micro-operation that is ready for issue in the picking cycle. The third micro-operation is picked from the remaining entries across the first set of entries and the second set of entries. The third micro-operation issues in a next picking cycle.
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公开(公告)号：US09910638B1
公开(公告)日：2018-03-06
申请号：US15247416
申请日：2016-08-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Hanbing Liu , John Kelley , Michael Estlick , Erik Swanson , Jay Fleischman
CPC classification number: G06F7/5525 , G06F7/535 , G06F2207/5523
Abstract: Square root operations in a computer processor are disclosed. A first iteration for calculating partial results of a square root operation is performed in a larger number of cycles than remaining iterations. The first iteration requires calculation of a first digit that is larger than the subsequent digits. The first iteration thus requires multiplication of values that are larger than corresponding values for the subsequent other digits. By splitting the first digit into two parts, the required multiplications can be performed in less time than if the first digit were not split. Performing these multiplications in less time reduces the total delay for clock cycles associated with the first digit calculations, which increases the possible clock frequency allowed. A multiply-and-accumulate unit that performs either packed-single operations or double-precision operations may be used, along with a combined division/square root unit for simultaneous execution of division and square root operations.
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公开(公告)号：US20180060039A1
公开(公告)日：2018-03-01
申请号：US15247416
申请日：2016-08-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Hanbing Liu , John Kelley , Michael Estlick , Erik Swanson , Jay Fleischman
CPC classification number: G06F7/5525 , G06F7/535 , G06F2207/5523
Abstract: Square root operations in a computer processor are disclosed. A first iteration for calculating partial results of a square root operation is performed in a larger number of cycles than remaining iterations. The first iteration requires calculation of a first digit that is larger than the subsequent digits. The first iteration thus requires multiplication of values that are larger than corresponding values for the subsequent other digits. By splitting the first digit into two parts, the required multiplications can be performed in less time than if the first digit were not split. Performing these multiplications in less time reduces the total delay for clock cycles associated with the first digit calculations, which increases the possible clock frequency allowed. A multiply-and-accumulate unit that performs either packed-single operations or double-precision operations may be used, along with a combined division/square root unit for simultaneous execution of division and square root operations.
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公开(公告)号：US09317250B2
公开(公告)日：2016-04-19
申请号：US13674220
申请日：2012-11-12
Applicant: Advanced Micro Devices, Inc.
Inventor： Kelvin D. Goveas , Debjit Das Sarma , Scott A. Hilker , Hanbing Liu
CPC classification number: G06F7/483 , G06F7/49936 , G06F7/5443
Abstract: The present application provides a method and apparatus for supporting denormal numbers in a floating point multiply-add unit (FMAC). One embodiment of the FMAC is configurable to add a product of first and second operands to a third operand. This embodiment of the FMAC is configurable to determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product. This embodiment of the FMAC is also configurable to cause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum.
Abstract translation: 本申请提供了一种用于支持浮点乘法单元（FMAC）中的反常数的方法和装置。 FMAC的一个实施例可配置为将第一和第二操作数的乘积添加到第三操作数。 FMAC的该实施例可配置为通过从乘积的乘积指数减去最小正态指数来确定乘积和第三操作数之和的最小指数偏移。 如果FMAC的这个实施例如果第三操作数的第三指数小于或等于乘积指数并且最小指数移位小于或等于，则可配置为使表示和的位移动移位最小指数移位 到总和的预测左移。
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