Semiconductor package structure and method for manufacturing the same

    公开(公告)号:US11776887B2

    公开(公告)日:2023-10-03

    申请号:US17315064

    申请日:2021-05-07

    CPC classification number: H01L23/49838 H01L21/4814 H01L23/49827

    Abstract: The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor structure, a conductive trace and a tenting structure. The semiconductor structure has a first surface, a second surface and a third surface extending between the first surface and the second surface, and the first surface, the second surface and the third surface define a through-silicon via recessed from the first surface. The conductive trace is disposed adjacent to the first surface, the second surface and the third surface of the semiconductor structure. The tenting structure covering the TSV of the semiconductor structure. A cavity is defined by the tenting structure and the TSV.

    Semiconductor package device and method of manufacturing the same

    公开(公告)号:US11437292B2

    公开(公告)日:2022-09-06

    申请号:US16599772

    申请日:2019-10-11

    Abstract: A sensing module, a semiconductor device package and a method of manufacturing the same are provided. The sensing module includes a sensing device, a first protection film and a second protection film. The sensing device has an active surface and a sensing region disposed adjacent to the active surface of the sensing device. The first protection film is disposed on the active surface of the sensing device and fully covers the sensing region. The second protection film is in contact with the first protection film and the active surface of the sensing device.

    Semiconductor package structure and method for manufacturing the same

    公开(公告)号:US11427466B2

    公开(公告)日:2022-08-30

    申请号:US16517444

    申请日:2019-07-19

    Abstract: A semiconductor package structure includes an electronic device having an exposed region adjacent to a first surface, a dam surrounding the exposed region of the semiconductor die and disposed on the first surface, the dam having a top surface away from the first surface, an encapsulant encapsulating the first surface of the electronic device, exposing the exposed region of the electronic device. A surface of the dam is retracted from a top surface of the encapsulant. A method for manufacturing the semiconductor package structure is also provided.

    Electronic component including a conductive pillar and method of manufacturing the same

    公开(公告)号:US10818627B2

    公开(公告)日:2020-10-27

    申请号:US15690143

    申请日:2017-08-29

    Abstract: An electronic component includes a die, a first protective layer, a second protective layer, a first conductive pillar and a second conductive pillar. The die includes a conductive pad. The first protective layer is disposed on the die. The first protective layer defines a first opening to expose the conductive pad of the die. The second protective layer is disposed on the first protective layer. The second protective layer defines a second opening and a first recess. The second opening exposes the conductive pad of the die. The first conductive pillar is disposed within the second opening and electrically connected to the conductive pad. The second conductive pillar is disposed within the first recess. A height of the first conductive pillar is substantially equal to a height of the second conductive pillar. A bottom surface of the first recess is disposed between a top surface of the first protective layer and a top surface of the second protective layer.

    Semiconductor device and semiconductor package

    公开(公告)号:US11600590B2

    公开(公告)日:2023-03-07

    申请号:US16362347

    申请日:2019-03-22

    Abstract: A semiconductor device and a semiconductor package including the same are provided. The semiconductor device includes a semiconductor element; a protective layer disposed adjacent to the surface of the semiconductor element, the protective layer defining an opening to expose the semiconductor element; a first bump disposed on the semiconductor element; and a second bump disposed onto the surface of the protective layer. The first bump has a larger cross-section surface area than the second bump.

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