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公开(公告)号：US09673962B1
公开(公告)日：2017-06-06
申请号：US15045826
申请日：2016-02-17
Applicant: Analog Devices Global
CPC classification number: H04L7/0008 , H04L7/033 , H04L7/0331 , H04L7/046
Abstract: An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.
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公开(公告)号：US20170264422A1
公开(公告)日：2017-09-14
申请号：US15605082
申请日：2017-05-25
Applicant: Analog Devices Global
Inventor： Muhammad Kalimuddin Khan , Kenneth J. Mulvaney , Philip P.E. Quinlan , Shane O'Mahony
CPC classification number: H04L7/0008 , H04L7/033 , H04L7/0331 , H04L7/046
Abstract: An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.
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公开(公告)号：US10129011B2
公开(公告)日：2018-11-13
申请号：US15605082
申请日：2017-05-25
Applicant: Analog Devices Global
Abstract: An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.
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