Bit error rate timer for a dynamic latch
    1.
    发明授权
    Bit error rate timer for a dynamic latch 有权
    动态锁存器的位错误率定时器

    公开(公告)号:US08860598B2

    公开(公告)日:2014-10-14

    申请号:US13839972

    申请日:2013-03-15

    CPC classification number: H03M1/145 H03M1/36 H03M1/46

    Abstract: A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions.

    Abstract translation: A转换器系统,包括对输入信号的第一部分进行数字化的第一转换器,第一转换器包括比较器,具有模拟第一转换器中的比较器的电路结构的电路结构的定时器,定时器接收输入 信号,其指示比较器中的操作开始;第二转换器,响应于来自定时器的输出,数字化从第一部分剩余的输入信号的第二部分;以及组合器,具有从第一数字化生成数字代码的输入, 第二部分。

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