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公开(公告)号：US12126354B2
公开(公告)日：2024-10-22
申请号：US18206666
申请日：2023-06-07
Applicant: SIGMASENSE, LLC.
Inventor： Phuong Huynh
CPC classification number: H03M1/46 , H02J50/001 , H02J50/20 , H04B5/48 , H04B5/79
Abstract: A batteryless wireless sensor system includes a data acquisition system, a radio frequency (RF) transceiver, and a batteryless wireless sensor device. The RF transceiver is in communication with the data acquisition system, transmits a RF signal, and receives sensor data and provide the sensor data to the data acquisition system. The batteryless wireless sensor device includes a RF transmitter, an analog to digital converter (ADC), and a sensor. The batteryless wireless sensor harvests energy from the RF signal and generates a DC signal based on the energy harvested from the RF signal, powers up and operates the ADC and the sensor based on the DC signal, and generates sensor data. The batteryless wireless sensor then transmits the sensor data via the RF transmitter to the RF transceiver. In certain examples, the ADC is implemented as a current mode ADC.
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公开(公告)号：US12107595B2
公开(公告)日：2024-10-01
申请号：US17906663
申请日：2021-03-23
Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Inventor： Yuki Yagishita
Abstract: A kickback current is suppressed so as not to generate a deviation in a signal that outputs a comparison result.
A comparator includes a first input terminal and a second input terminal to which a first differential input signal pair is input, a third input terminal and a fourth input terminal to which a second differential input signal pair is input, a first comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a positive side and connecting the second input terminal to a negative side and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and connecting the fourth input terminal to a negative side, and a second comparison circuit that outputs a signal corresponding to a difference signal of the first differential input signal pair generated by connecting the first input terminal to a negative side and connecting the second input terminal to a positive side, and a difference signal of the second differential input signal pair generated by connecting the third input terminal to a positive side and connecting the fourth input terminal to a negative side.-
公开(公告)号：US12081888B2
公开(公告)日：2024-09-03
申请号：US17660084
申请日：2022-04-21
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Alexandre Mas , Abdessamed Mekki , Cedric Tubert
IPC: H04N25/75 , H03M1/12 , H03M1/46 , H04N25/625 , H04N25/677
CPC classification number: H04N25/75 , H03M1/1245 , H03M1/46 , H04N25/625 , H04N25/677
Abstract: The present disclosure relates to a read-out circuit comprising N inputs configured to be connected to N respective outputs of a pixel array of an image sensor, with N being an integer strictly greater than 1; and N analog-to-digital converters organized in K groups, with K being an integer strictly greater than 1 and strictly less than N, and each having a first input coupled to a respective one of the N inputs and a second input. In each group, the second inputs of the analog-to-digital converters of the group are connected together, electrically decoupled from the second inputs of the analog-to-digital converters of the other groups, and configured to receive a first reference signal that is identical for all the analog-to-digital converters of the group.
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4.发明授权公开(公告)号：US12074609B2
公开(公告)日：2024-08-27
申请号：US17687765
申请日：2022-03-07
Applicant: Regents of the University of Minnesota
Inventor： Zhi Yang , Anh Tuan Nguyen , Diu Khue Luu , Jian Xu
Abstract: A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components.
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公开(公告)号：US12047087B2
公开(公告)日：2024-07-23
申请号：US17771268
申请日：2019-10-31
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Tadashi Minotani , Kenichi Matsunaga
Abstract: An AD converter includes: an accumulation conversion unit that performs a comparison of magnitudes of an input voltage V2 and an accumulated voltage V1 obtained by accumulating a unit voltage and outputs a comparison signal representing a result of the comparison; an accumulation comparison determination unit that repeatedly compares an accumulated voltage V1, obtained by repeating the comparison until the comparison signal changes and corresponding to an accumulated voltage V1 at which the comparison signal changes, and the input voltage V2 a predetermined number of times to determine an equivalent-state accumulation number in which a state probability that the comparison signal changes is equal to a threshold; and a control unit that determines conversion data of the input voltage using the equivalent-state accumulation number.
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Patent Agency Ranking
公开(公告)号：US20240231758A1
公开(公告)日：2024-07-11
申请号：US18417868
申请日：2024-01-19
Applicant: Apple Inc.
Inventor： Shahzad Nazar , Bharan Giridhar , Mohamed H. Abu-Rahma , Ajay Bhatia , Mayur V. Joshi , Yildiz Sinangil , Aravind Kandala
CPC classification number: G06F7/5443 , G06F7/523 , G06F17/15 , H03M1/46 , G06N20/00
Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit. By performing computation on global rather than local bit lines, standard data storage cells can be employed, improving the area efficiency of the compute-memory circuit.
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公开(公告)号：US11984900B2
公开(公告)日：2024-05-14
申请号：US17934654
申请日：2022-09-23
Applicant: QUALCOMM Incorporated
Inventor： Jianjun Yu , Yue Chao , Tomas O'Sullivan , Lai Kan Leung
IPC: H03L7/099 , H03B5/12 , H03K3/0231 , H03M1/46
CPC classification number: H03L7/099 , H03B5/1293 , H03K3/0231 , H03M1/46
Abstract: Methods and apparatus for storing a control voltage of a phased-locked loop (PLL) when switching from mission mode to standby mode for the PLL, and for restoring the control voltage of the PLL when switching back to mission mode. An example PLL circuit includes a charge pump, a voltage-controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node, and a tracking circuit coupled to the node. The tracking circuit is generally configured to sample a voltage of the node during a mission mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node for reentering the mission mode using the saved representation of the sampled voltage.
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公开(公告)号：US20230370083A1
公开(公告)日：2023-11-16
申请号：US18022071
申请日：2021-06-15
Inventor： Koji OBATA
IPC: H03M1/46
CPC classification number: H03M1/46
Abstract: A comparator compares a differential voltage between a voltage to be converted as an analog input voltage and a comparative voltage generated by a D/A converting unit with a comparison reference voltage. A switching circuit selectively connects a capacitor, associated with the analog input voltage selected as the voltage to be converted, to an output terminal of an integrator. The integrator integrates the differential voltage in a state where an A/D converting section has performed conversion operation on a least significant bit. A comparison reference voltage generating unit uses, as the comparison reference voltage, a charge voltage for the capacitor associated with the analog input voltage selected as the voltage to be converted.
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公开(公告)号：US11647306B2
公开(公告)日：2023-05-09
申请号：US17521911
申请日：2021-11-09
Inventor： Yusuke Tokunaga
IPC: H04N5/365 , H03M1/46 , H04N5/3745 , H04N5/376 , H04N5/378
CPC classification number: H04N5/3655 , H03M1/46 , H04N5/378 , H04N5/3765 , H04N5/37452 , H04N5/37455
Abstract: A solid-state imaging device includes: a pixel unit that outputs a pixel signal corresponding to an amount of incident light; an A/D converter that performs A/D conversion on the pixel signal; and a D/A conversion circuit that generates a reference signal to be used by the A/D converter. The D/A conversion circuit includes a first buffer circuit that outputs a base voltage VTOP for generating the reference signal, and the first buffer circuit includes a differential pair circuit including a first transistor and a second transistor, and a suppression circuit that suppresses a variation in the base voltage by canceling out a characteristic difference between the first transistor and the second transistor.
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公开(公告)号：US10084467B1
公开(公告)日：2018-09-25
申请号：US15861624
申请日：2018-01-03
Inventor： Soon-Jyh Chang , Wen-Chia Luo , Yi-Lun Chiang , Chuo-Ming Kuo
CPC classification number: H03M1/1245 , H03M1/129 , H03M1/1295 , H03M1/38 , H03M1/46
Abstract: An interfacing circuit adaptable to an analog-to-digital converter (ADC) includes a sample and hold (S/H) circuit; an input switch; an input capacitor with a first end connected to an input end of a comparator of the ADC via the S/H circuit, and with a second end connected to receive an input signal via the input switch; a hold switch connected between the second end of the input capacitor and an original common-mode voltage; a reset switch connected between the input end of the comparator and a target common-mode voltage; and a front switch connected between the first end of the input capacitor and the target common-mode voltage.
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