公开(公告)号：US09311967B2

公开(公告)日：2016-04-12

申请号：US14291582

申请日：2014-05-30

Applicant: Apple Inc.

Inventor： Ajay Kumar Bhatia ,  Anshul Y. Mehta ,  Amrinder S. Barn ,  Greg M. Hess

IPC: G11C5/14 ,  G11C7/00 ,  G11C29/02 ,  G11C29/52 ,  G11C29/04 ,  G11C29/44

CPC classification number: G11C5/147 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled to the plurality of memory cells. The control circuitry may be configured to select one of the voltage reduction circuits based on one or more operating parameters. The control circuitry may be further configured to activate the selected voltage reduction circuit upon receiving a write command directed towards the memory cells. The control circuitry may be further configured to execute the write command. Upon completion of the write command, the control circuitry may be further configured to de-activate the selected one of the voltage reduction circuits.

Abstract translation: 可以想到一种系统，存储器件和方法，其中该装置可以包括多个存储器单元，多个电压降低电路和控制电路。 多个电压降低电路可以被配置为降低耦合到多个存储器单元的电源的电压电平。 控制电路可以被配置为基于一个或多个操作参数来选择一个电压降低电路。 控制电路还可以被配置为在接收到针对存储器单元的写入命令时激活所选择的电压降低电路。 控制电路还可以被配置为执行写命令。 在完成写入命令之后，控制电路还可以被配置为去激活所选择的一个电压降低电路。

公开(公告)号：US20150348600A1

公开(公告)日：2015-12-03

申请号：US14291582

申请日：2014-05-30

Applicant: Apple Inc.

Inventor： Ajay Kumar Bhatia ,  Anshul Y. Mehta ,  Amrinder S. Barn ,  Greg M. Hess

IPC: G11C5/14 ,  G11C7/00

CPC classification number: G11C5/147 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled to the plurality of memory cells. The control circuitry may be configured to select one of the voltage reduction circuits based on one or more operating parameters. The control circuitry may be further configured to activate the selected voltage reduction circuit upon receiving a write command directed towards the memory cells. The control circuitry may be further configured to execute the write command. Upon completion of the write command, the control circuitry may be further configured to de-activate the selected one of the voltage reduction circuits.

Abstract translation: 可以想到一种系统，存储器件和方法，其中该装置可以包括多个存储器单元，多个电压降低电路和控制电路。 多个电压降低电路可以被配置为降低耦合到多个存储器单元的电源的电压电平。 控制电路可以被配置为基于一个或多个操作参数来选择一个电压降低电路。 控制电路还可以被配置为在接收到针对存储器单元的写入命令时激活所选择的电压降低电路。 控制电路还可以被配置为执行写命令。 在完成写入命令之后，控制电路还可以被配置为去激活所选择的一个电压降低电路。