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公开(公告)号：US20210142863A1
公开(公告)日：2021-05-13
申请号：US16677470
申请日：2019-11-07
申请人： Apple Inc.
IPC分类号： G11C29/50 , G11C11/419 , G11C11/409 , G11C29/12
摘要： An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.
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公开(公告)号：US11688486B2
公开(公告)日：2023-06-27
申请号：US17402915
申请日：2021-08-16
申请人： Apple Inc.
IPC分类号： G11C5/14 , G11C29/50 , G11C11/419 , G11C29/12 , G11C11/409
CPC分类号： G11C29/50016 , G11C11/409 , G11C11/419 , G11C29/12005 , G11C2029/5004
摘要： An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.
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公开(公告)号：US10340900B2
公开(公告)日：2019-07-02
申请号：US15389332
申请日：2016-12-22
申请人： Apple Inc.
发明人： Amrinder S. Barn , Bo Zhao , Michael A. Dreesen
摘要： In an embodiment, an apparatus includes a first latch including a true storage node and a complement storage node, a discharge circuit, and a second latch. The first latch may pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal. The discharge circuit may, in response to a determination that a scan mode signal is asserted, selectively discharge either the true storage node or the complement storage node based on a value of a scan data signal, and otherwise may selectively discharge either the true storage node or the complement storage node based on a value of a data signal. The second latch may store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node.
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公开(公告)号：US10523194B2
公开(公告)日：2019-12-31
申请号：US15717276
申请日：2017-09-27
申请人： Apple Inc.
发明人： Jaroslav Raszka , Amrinder S. Barn , Victor Zyuban , Shingo Suzuki , Ajay Kumar Bhatia , Mohamed H. Abu-Rahma , Shahzad Nazar , Greg M. Hess
IPC分类号： H03K17/16 , H03K17/14 , H03K19/00 , H03K19/003
摘要： A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.
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公开(公告)号：US09311967B2
公开(公告)日：2016-04-12
申请号：US14291582
申请日：2014-05-30
申请人： Apple Inc.
CPC分类号： G11C5/147 , G11C29/021 , G11C29/028 , G11C29/52 , G11C2029/0409 , G11C2029/4402
摘要： A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled to the plurality of memory cells. The control circuitry may be configured to select one of the voltage reduction circuits based on one or more operating parameters. The control circuitry may be further configured to activate the selected voltage reduction circuit upon receiving a write command directed towards the memory cells. The control circuitry may be further configured to execute the write command. Upon completion of the write command, the control circuitry may be further configured to de-activate the selected one of the voltage reduction circuits.
摘要翻译： 可以想到一种系统，存储器件和方法，其中该装置可以包括多个存储器单元，多个电压降低电路和控制电路。 多个电压降低电路可以被配置为降低耦合到多个存储器单元的电源的电压电平。 控制电路可以被配置为基于一个或多个操作参数来选择一个电压降低电路。 控制电路还可以被配置为在接收到针对存储器单元的写入命令时激活所选择的电压降低电路。 控制电路还可以被配置为执行写命令。 在完成写入命令之后，控制电路还可以被配置为去激活所选择的一个电压降低电路。
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公开(公告)号：US20220028479A1
公开(公告)日：2022-01-27
申请号：US17402915
申请日：2021-08-16
申请人： Apple Inc.
IPC分类号： G11C29/50 , G11C11/419 , G11C11/409 , G11C29/12
摘要： An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.
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公开(公告)号：US20180181193A1
公开(公告)日：2018-06-28
申请号：US15389332
申请日：2016-12-22
申请人： Apple Inc.
发明人： Amrinder S. Barn , Bo Zhao , Michael A. Dreesen
IPC分类号： G06F1/32 , H03K19/0175 , H03K3/356 , G11C7/10
CPC分类号： H03K3/356104 , G11C7/106 , G11C29/32 , G11C2029/3202 , H03K3/356121 , H03K19/017509
摘要： In an embodiment, an apparatus includes a first latch including a true storage node and a complement storage node, a discharge circuit, and a second latch. The first latch may pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal. The discharge circuit may, in response to a determination that a scan mode signal is asserted, selectively discharge either the true storage node or the complement storage node based on a value of a scan data signal, and otherwise may selectively discharge either the true storage node or the complement storage node based on a value of a data signal. The second latch may store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node.
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公开(公告)号：US11094395B2
公开(公告)日：2021-08-17
申请号：US16677470
申请日：2019-11-07
申请人： Apple Inc.
IPC分类号： G11C5/14 , G11C29/50 , G11C11/419 , G11C29/12 , G11C11/409
摘要： An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.
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公开(公告)号：US20190097622A1
公开(公告)日：2019-03-28
申请号：US15717276
申请日：2017-09-27
申请人： Apple Inc.
发明人： Jaroslav Raszka , Amrinder S. Barn , Victor Zyuban , Shingo Suzuki , Ajay Kumar Bhatia , Mohamed H. Abu-Rahma , Shahzad Nazar , Greg M. Hess
IPC分类号： H03K17/16
CPC分类号： H03K17/162 , H03K17/145 , H03K19/0016 , H03K19/00369 , H03K2217/0027 , H03K2217/0036
摘要： A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.
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公开(公告)号：US20150348600A1
公开(公告)日：2015-12-03
申请号：US14291582
申请日：2014-05-30
申请人： Apple Inc.
CPC分类号： G11C5/147 , G11C29/021 , G11C29/028 , G11C29/52 , G11C2029/0409 , G11C2029/4402
摘要： A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled to the plurality of memory cells. The control circuitry may be configured to select one of the voltage reduction circuits based on one or more operating parameters. The control circuitry may be further configured to activate the selected voltage reduction circuit upon receiving a write command directed towards the memory cells. The control circuitry may be further configured to execute the write command. Upon completion of the write command, the control circuitry may be further configured to de-activate the selected one of the voltage reduction circuits.
摘要翻译： 可以想到一种系统，存储器件和方法，其中该装置可以包括多个存储器单元，多个电压降低电路和控制电路。 多个电压降低电路可以被配置为降低耦合到多个存储器单元的电源的电压电平。 控制电路可以被配置为基于一个或多个操作参数来选择一个电压降低电路。 控制电路还可以被配置为在接收到针对存储器单元的写入命令时激活所选择的电压降低电路。 控制电路还可以被配置为执行写命令。 在完成写入命令之后，控制电路还可以被配置为去激活所选择的一个电压降低电路。
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