-
公开(公告)号：US20190252012A1
公开(公告)日：2019-08-15
申请号：US16396215
申请日：2019-04-26
申请人： SK hynix Inc.
发明人： Young-Dong ROH
CPC分类号： G11C7/222 , G06F3/0614 , G06F3/0629 , G06F3/0659 , G11C7/062 , G11C7/1072 , G11C8/06 , G11C8/18 , G11C29/023 , G11C29/028 , G11C29/36 , G11C29/52 , G11C2207/2254
摘要： A memory system may include: a controller suitable for: generating a first clock and first pattern data having a first phase difference, in a write calibration mode, calibrating, the first phase difference depending on a second information, in a read calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, a first information according to comparing of the first and second values, receiving by calibrating, a second phase difference generated by a memory device depending on the first information; and the memory device suitable for: generating the second clock and the second pattern data having the second phase difference, in the write calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, the second information according to comparing of the first and second values.
-
2.发明申请公开(公告)号：US20190220353A1
公开(公告)日：2019-07-18
申请号：US16361200
申请日：2019-03-21
申请人： Silicon Motion Inc.
发明人： Tsung-Chieh Yang , Hong-Jung Hsu
CPC分类号： G06F11/1072 , G06F3/0604 , G06F3/0619 , G06F3/064 , G06F3/0688 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C16/16 , G11C16/26 , G11C29/52 , G11C2211/5641
摘要： A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.
-
公开(公告)号：US20190215019A1
公开(公告)日：2019-07-11
申请号：US16352540
申请日：2019-03-13
发明人： Takuya HAGA
IPC分类号： H03M13/45 , H03M13/00 , H03M13/11 , G06F11/10 , G11C11/56 , G11C16/14 , G11C29/52 , G11C16/34 , G11C16/26
CPC分类号： H03M13/458 , G06F11/1012 , G06F11/1068 , G11C11/5642 , G11C16/14 , G11C16/16 , G11C16/26 , G11C16/349 , G11C29/52 , G11C2029/0411 , H03M13/1111 , H03M13/45 , H03M13/6325
摘要： A memory system includes a nonvolatile semiconductor memory and a controller. The controller is configured to maintain a plurality of log likelihood ratio (LLR) tables for predicting a value of data read from the nonvolatile semiconductor memory, count a number of times that each of write operations, erase operations, and read operations have been carried out with respect to each unit storage region of the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on the counted number of the read operations and one of the counted number of the write operations and the counted number of the erase operations, which correspond to a target unit storage region of a read operation, and carry out decoding of data read from the target unit storage region of the read operation, using one of the LLR tables selected according to the determined order.
-
公开(公告)号：US20190215016A1
公开(公告)日：2019-07-11
申请号：US15868868
申请日：2018-01-11
CPC分类号： H03M13/35 , G06F3/0616 , G06F3/0652 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G11C29/52
摘要： A data storage system capable of switching a code rate based on a host command is disclosed. A controller of the data storage system may set a code rate in a data storage device to a first code rate for encoding data to be written to non-volatile memory of the data storage device. The controller may receive, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate. The controller may switch the set code rate from the first code rate to the second code rate at the indicated switch point.
-
公开(公告)号：US20190215015A1
公开(公告)日：2019-07-11
申请号：US16357696
申请日：2019-03-19
发明人： Shinichi KANNO , Hironori UCHIKAWA
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
-
公开(公告)号：US20190213074A1
公开(公告)日：2019-07-11
申请号：US16240266
申请日：2019-01-04
发明人： Aman BHATIA , Naveen KUMAR , Fan ZHANG
CPC分类号： G06F11/1072 , G06F11/1004 , G11C7/1006 , G11C11/5628 , G11C29/42 , G11C29/52 , G11C2211/5641 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/2909
摘要： Encoding methods and systems are provided for a memory device including quadruple-level cell (QLC) memory cells. A controller of a memory system includes a first encoder and a second encoder. The first encoder encodes, based on a constrained code, a first group of data to generate a third group of data, the first group of data corresponding to first and third logical pages among a plurality of logical pages. The second encoder encodes, based on a Gray code, a second group of data and the third group of data to generate encoded sequences corresponding to a plurality of program-voltage (PV) levels, the second group of data corresponding to the second and fourth logical pages among the plurality of logical pages.
-
公开(公告)号：US20190196904A1
公开(公告)日：2019-06-27
申请号：US16056897
申请日：2018-08-07
申请人： SK hynix Inc.
发明人： Sung-Ho KIM
CPC分类号： G06F11/1068 , G11C29/52 , H03M13/2906
摘要： A memory device includes: a non-volatile memory circuit suitable for storing defective column information; a defective latch circuit suitable for receiving and storing the defective column information from the non-volatile memory circuit during a boot-up operation; an error correction code generation circuit suitable for generating an error correction code for correcting an error of the defective column information based on the defective column information; an error correction code latch circuit suitable for storing the error correction code; an error correction circuit suitable for correcting an error of the defective column information transferred from the defective latch circuit based on the error correction code which is transferred from the error correction code latch circuit so as to produce an error-corrected defective column information; and a memory bank suitable for performing a column repair operation based on the error-corrected defective column information.
-
公开(公告)号：US20190188076A1
公开(公告)日：2019-06-20
申请号：US16223136
申请日：2018-12-18
发明人： Ho-Yin Chen , Ting-Feng Chang , Chun-Chia Chen
CPC分类号： G06F11/1068 , G11C29/52
摘要： A memory with an error correction function includes a controller and a memory cell array. The controller optionally writes written data to a normal storage area and a backup area of the memory cell array, and when the controller reads first data corresponding to the written data from the normal storage area, if at least two errors are included in the first data, the controller reads the backup area to output second data corresponding to the written data from the backup area.
-
公开(公告)号：US20190163566A1
公开(公告)日：2019-05-30
申请号：US15828425
申请日：2017-11-30
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/065 , G06F3/0689 , G06F11/1068 , G06F11/108 , G11C29/52 , G11C2029/0411
摘要： Systems, apparatuses, methods, and computer program products are disclosed for updating data of write-in-place storage devices. One system includes a write-in-place memory device including a redundant storage structure and a controller for the memory device. A memory device is configured to store data across a set of stripes of a redundant storage structure. A controller is configured to receive updated data for a dataset stored across a first stripe, generate a new parity for the dataset based on the updated data, overwrite the dataset across the first stripe with the updated data, and/or write the new parity to the set of stripes.
-
公开(公告)号：US20190156896A1
公开(公告)日：2019-05-23
申请号：US16043964
申请日：2018-07-24
发明人： Ji-Yoon Park , Wan-Dong Kim , Seung-Bum Kim , Deok-Woo Lee , You-Se Kim , Se-Hwan Park , Jin-Woo Park
CPC分类号： G11C16/16 , G11C11/5635 , G11C16/0483 , G11C16/32 , G11C16/3445 , G11C29/52
摘要： A method of erasing a memory device, the method of erasing the memory device including: performing, in a first erase period, a first erase operation on memory cells respectively connected to a plurality of word lines, wherein at least one of the memory cells, which is included in a memory block, is not erase-passed; determining, after the first erase period, an erase operation speed by applying a verify voltage to at least one of the plurality of word lines, and determining an effective erasing time for each word line based on the determined erase operation speed; and performing, in a second erase period, a second erase operation on the memory cells respectively connected to the plurality of word lines based on the determined effective erasing times.
-
-
-
-
-
-
-
-
-
搜索结果
3365 条记录 (耗时 0.14 秒)