公开(公告)号：US11500638B1

公开(公告)日：2022-11-15

申请号：US16739464

申请日：2020-01-10

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  James Vash ,  Pradeep Kanapathipillai ,  Mridul Agarwal ,  Zhaoming Hu ,  Tyler Huberty ,  Charles Tucker

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

Abstract: A method and system for compressing and decompressing data is disclosed. A compression command may initiate the prefetching of first data, which may be stored in a first buffer. Multiple words of the first data may be read from the first buffer and used to generate a plurality of compressed packets, each of which includes a command specifying a type of packet. The compressed packets may be combined into a group and multiple groups may be combined and stored in a second buffer. A decompression command may initiate the prefetching of second data, which is stored in the first buffer. A portion of the second data may be read from the first buffer and used to generate a group of compressed packets. Multiple output words may be generated dependent upon the group of compressed packets.

公开(公告)号：US09875214B2

公开(公告)日：2018-01-23

申请号：US14814590

申请日：2015-07-31

Applicant: ARM LIMITED ,  APPLE, INC.

Inventor： Mbou Eyole ,  Nigel John Stephens ,  Jeffry Gonion ,  Alex Klaiber ,  Charles Tucker

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/38 ,  G06F15/80

CPC classification number: G06F15/8076 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30192 ,  G06F9/345 ,  G06F9/3455 ,  G06F9/355 ,  G06F9/3887

Abstract: An apparatus and method are provided for transferring a plurality of data structures between memory and a plurality of vector registers, each vector register being arranged to store a vector operand comprising a plurality of data elements. Access circuitry is used to perform access operations to move data elements of vector operands between the data structures in memory and specified vector registers, each data structure comprising multiple data elements stored at contiguous addresses in the memory. Decode circuitry is responsive to a single access instruction identifying a plurality of vector registers and a plurality of data structures that are located discontiguously with respect to each other in the memory, to generate control signals to control the access circuitry to perform a sequence of access operations to move the plurality of data structures between the memory and the plurality of vector registers such that the vector operand in each vector register holds a corresponding data element from each of the plurality of data structures. This provides a very efficient mechanism for performing complex access operations, resulting in an increase in execution speed, and potential reductions in power consumption.