公开(公告)号：US09672305B1

公开(公告)日：2017-06-06

申请号：US14607278

申请日：2015-01-28

Applicant: Apple Inc.

Inventor： Suparn Vats ,  Daniel J. Flees ,  Rohit Kumar

IPC: G06F17/50 ,  H03L7/00 ,  G06F1/32

CPC classification number: G06F17/505 ,  G06F1/3237 ,  G06F17/50 ,  G06F17/5022 ,  G06F17/5036 ,  G06F17/5045 ,  G06F17/5059 ,  G06F2217/62 ,  G06F2217/78 ,  G06F2217/84 ,  H03L7/00

Abstract: A method for designing clock gates which may reduce timing requirements associated with clock gating control signals may include identifying a clock gating function included in a Hardware Description Language of an integrated circuit, wherein the clock gating function may include capturing a state of an enable signal dependent upon a clock signal. The method may include determining a delay time for capturing the state of the enable signal dependent on a time difference between transitions of the enable signal and the clock signal. The method may include creating a gating circuit, in which the gating circuit includes a delay unit coupled to a source of the clock signal, and wherein a delay value is dependent upon the amount of time to delay capturing the enable signal. The method may include modifying the HDL model dependent upon the clock gating circuit.