公开(公告)号：US11740676B2

公开(公告)日：2023-08-29

申请号：US17821394

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/00 ,  G06F1/3209 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287

CPC classification number: G06F1/3209 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/00

Abstract: An integrated circuit may include multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g., to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

公开(公告)号：US11422606B2

公开(公告)日：2022-08-23

申请号：US17177521

申请日：2021-02-17

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/00 ,  G06F1/3209 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287

Abstract: An integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

公开(公告)号：US09606605B2

公开(公告)日：2017-03-28

申请号：US14200216

申请日：2014-03-07

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/32

CPC classification number: G06F1/3209 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

公开(公告)号：US09411404B2

公开(公告)日：2016-08-09

申请号：US14157171

申请日：2014-01-16

Applicant: Apple Inc.

Inventor： Rohit Kumar ,  Suresh Periyacheri

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3243 ,  G06F1/3293 ,  G06F9/5094 ,  Y02D10/122 ,  Y02D10/152 ,  Y02D10/22

Abstract: An apparatus is disclosed for managing operational modes of a processor. The apparatus may include the processor which may include a coprocessor, an instruction queue, and a monitoring circuit for detecting instructions for the coprocessor in the instruction queue. The monitoring circuit may detect when the instruction queue holds no instructions for the coprocessor. If the instruction queue holds no instructions for the coprocessor, the coprocessor may be placed into a mode in which the coprocessor consumes less power. The monitoring circuit may detect an instruction for the coprocessor in the instruction queue. In response to the instruction for the coprocessor, the coprocessor may be placed into a mode in which the coprocessor may execute the instruction.

Abstract translation: 公开了一种用于管理处理器的操作模式的装置。 该装置可以包括可以包括协处理器，指令队列和用于检测指令队列中的协处理器的指令的监视电路的处理器。 监视电路可以检测指令队列何时不保存协处理器的指令。 如果指令队列不保存协处理器的指令，协处理器可以被置于协处理器消耗更少功率的模式中。 监视电路可以检测指令队列中协处理器的指令。 响应于协处理器的指令，协处理器可以被置于协处理器可以执行指令的模式中。

公开(公告)号：US20150033045A1

公开(公告)日：2015-01-29

申请号：US13948843

申请日：2013-07-23

Applicant: Apple Inc.

Inventor： Pankaj Raghuvanshi ,  Rohit Kumar ,  Suresh Periyacheri

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3836 ,  G06F9/4893 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/24

Abstract: An apparatus for performing instruction throttling for a computing system is disclosed. The apparatus may include a first counter, a second counter, and a control circuit. The second counter may be configured to increment in response to a determination that a processing cycle of a processor has completed. The control circuit may be configured to initialize the first and second counters, detect the processor has issued and instruction, decrement the first counter in response to the detection of the issued instruction, block the processor from issuing instructions dependent upon the a value of the first counter, reset the first counter dependent upon a value of the second counter, and reset the second counter in response to a determination that the value of the second counter is greater than a pre-determined value.

Abstract translation: 公开了一种用于对计算系统执行指令调节的装置。 该装置可以包括第一计数器，第二计数器和控制电路。 第二计数器可以被配置为响应于处理器的处理周期的确定已经完成而递增。 控制电路可以被配置为初始化第一和第二计数器，检测处理器已经发出和指令，响应于所发出的指令的检测而减小第一计数器，阻止处理器发出指令，取决于第一和第二计数器的值 计数器，根据第二计数器的值复位第一计数器，并且响应于第二计数器的值大于预定值的确定而复位第二计数器。

公开(公告)号：US12235703B2

公开(公告)日：2025-02-25

申请号：US18351248

申请日：2023-07-12

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/3209 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

Abstract: An integrated circuit may include multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances.

公开(公告)号：US20210173465A1

公开(公告)日：2021-06-10

申请号：US17177521

申请日：2021-02-17

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/3209 ,  G06F1/3206 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/3287

Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

公开(公告)号：US20170160791A1

公开(公告)日：2017-06-08

申请号：US15433201

申请日：2017-02-15

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/32

CPC classification number: G06F1/3209 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

公开(公告)号：US09672305B1

公开(公告)日：2017-06-06

申请号：US14607278

申请日：2015-01-28

Applicant: Apple Inc.

Inventor： Suparn Vats ,  Daniel J. Flees ,  Rohit Kumar

IPC: G06F17/50 ,  H03L7/00 ,  G06F1/32

CPC classification number: G06F17/505 ,  G06F1/3237 ,  G06F17/50 ,  G06F17/5022 ,  G06F17/5036 ,  G06F17/5045 ,  G06F17/5059 ,  G06F2217/62 ,  G06F2217/78 ,  G06F2217/84 ,  H03L7/00

Abstract: A method for designing clock gates which may reduce timing requirements associated with clock gating control signals may include identifying a clock gating function included in a Hardware Description Language of an integrated circuit, wherein the clock gating function may include capturing a state of an enable signal dependent upon a clock signal. The method may include determining a delay time for capturing the state of the enable signal dependent on a time difference between transitions of the enable signal and the clock signal. The method may include creating a gating circuit, in which the gating circuit includes a delay unit coupled to a source of the clock signal, and wherein a delay value is dependent upon the amount of time to delay capturing the enable signal. The method may include modifying the HDL model dependent upon the clock gating circuit.

公开(公告)号：US20150006916A1

公开(公告)日：2015-01-01

申请号：US13929331

申请日：2013-06-27

Applicant: Apple Inc.

Inventor： Matthias Knoth ,  Rohit Kumar ,  Eric Smith ,  Louis Luh

IPC: G06F1/26 ,  H02J1/10

CPC classification number: G06F1/26 ,  H02J1/02 ,  H02J1/10 ,  H02J7/345 ,  Y10T307/527

Abstract: In some embodiments, a system may include at least one voltage controller. At least one of the voltage controllers may assess, during use, an occurrence of a predetermined condition. In some embodiments, the system may include an at least first capacitor. The at least first capacitor may be coupled to at least one of the voltage controllers such that at least one of the voltage controllers engages the at least first capacitor to supply additional current when the predetermined condition occurs. When the increase in current is no longer required the at least first capacitor may be disengaged. The at least first capacitor may be charged when disengaged until a predetermined capacity.

Abstract translation: 在一些实施例中，系统可以包括至少一个电压控制器。 至少一个电压控制器可以在使用期间评估预定条件的发生。 在一些实施例中，系统可以包括至少第一电容器。 至少第一电容器可以耦合到至少一个电压控制器，使得当预定条件发生时，至少一个电压控制器接合至少第一电容器以提供附加电流。 当电流的增加不再需要时，可以使至少第一电容器分离。 至少第一电容器可以在分离直到预定容量时被充电。