公开(公告)号：US12081226B2

公开(公告)日：2024-09-03

申请号：US17931065

申请日：2022-09-09

Applicant: Apple Inc.

Inventor： Giovanni Saccomanno ,  Alberto Celin ,  Fabio Busignani ,  Siarhei Meliukh

IPC: H03M1/18 ,  H03M1/00 ,  H03M1/10 ,  H03M1/34

CPC classification number: H03M1/181 ,  H03M1/001 ,  H03M1/1071 ,  H03M1/34

Abstract: A tracking ADC with a feed-forward loop is disclosed. The tracking ADC includes a feedback circuit configured to generate a feedback signal using an input voltage and a comparison circuit configured to sample, using a plurality of threshold values, the feedback signal to generate a plurality of samples. A counter circuit is configured to update a count value using a subset of the plurality of samples. A digital-to-analog converter (DAC) circuit configured to generate a control signal using the count value. The feedback circuit is further configured to modify the feedback signal using the control signal and at least one of the plurality of samples. By modifying the feedback voltage, the settling time may be reduced, allowing the ADC to be run at a higher clock speed.

公开(公告)号：US20240088909A1

公开(公告)日：2024-03-14

申请号：US17931065

申请日：2022-09-09

Applicant: Apple Inc.

Inventor： Giovanni Saccomanno ,  Alberto Celin ,  Fabio Busignani ,  Siarhei Meliukh

IPC: H03M1/18 ,  H03M1/00 ,  H03M1/10 ,  H03M1/34

CPC classification number: H03M1/181 ,  H03M1/001 ,  H03M1/1071 ,  H03M1/34

Abstract: A tracking ADC with a feed-forward loop is disclosed. The tracking ADC includes a feedback circuit configured to generate a feedback signal using an input voltage and a comparison circuit configured to sample, using a plurality of threshold values, the feedback signal to generate a plurality of samples. A counter circuit is configured to update a count value using a subset of the plurality of samples. A digital-to-analog converter (DAC) circuit configured to generate a control signal using the count value. The feedback circuit is further configured to modify the feedback signal using the control signal and at least one of the plurality of samples. By modifying the feedback voltage, the settling time may be reduced, allowing the ADC to be run at a higher clock speed.