公开(公告)号：US20230361782A1

公开(公告)日：2023-11-09

申请号：US18245870

申请日：2021-09-27

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION

发明人： DAISUKE IDE ,  NOBUHIKO SHIGYO ,  KEITA KOMAGATA ,  HIROYUKI WATANABE ,  TAKAHIRO NAITO

IPC分类号： H03M1/12 ,  H03M1/18 ,  H03M1/34

CPC分类号： H03M1/181 ,  H03M1/1205 ,  H03M1/34

摘要： Provided is a low voltage and compact digital control regulator that achieves enhanced stability and reduced variations in ripple voltage and droop characteristics. The digital control regulator includes a first A/D converter configured to generate a first digital signal according to a differential voltage between an output voltage and a first reference voltage, an output stage circuit configured to generate the output voltage, a replica circuit having the same circuit configuration as the output stage circuit and configured to output a replica voltage related to the output voltage, a second A/D converter configured to generate a second digital signal according to a differential voltage between the replica voltage and a second reference voltage, and a control circuit configured to generate a control signal for controlling a gain of the output stage circuit, according to the first digital signal and the second digital signal.

公开(公告)号：US20180152198A1

公开(公告)日：2018-05-31

申请号：US15878907

申请日：2018-01-24

申请人： Cirrus Logic International Semiconductor Ltd.

发明人： John Paul LESSO ,  Emmanuel Philippe Christian HARDY

IPC分类号： H03M7/30 ,  H03M1/50 ,  H03M1/18 ,  H03K9/08 ,  H03K7/08 ,  H03M3/00

CPC分类号： H03M7/30 ,  H03K7/08 ,  H03K9/08 ,  H03M1/18 ,  H03M1/181 ,  H03M1/50 ,  H03M1/504 ,  H03M3/484

摘要： This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).

公开(公告)号：US09774342B1

公开(公告)日：2017-09-26

申请号：US14596826

申请日：2015-01-14

申请人： Cirrus Logic, Inc.

发明人： Edmund Mark Schneider ,  Aniruddha Satoskar ,  Daniel J. Allen ,  Seyedeh Maryam Mortazavi Zanjani

IPC分类号： H04R3/00 ,  H03M1/18 ,  H03M1/00 ,  H03M1/06 ,  H03M3/00 ,  G10K11/16

CPC分类号： H03M1/188 ,  G10K11/16 ,  H03M1/002 ,  H03M1/0631 ,  H03M1/18 ,  H03M1/181 ,  H03M3/466 ,  H04R3/02 ,  H04R3/04 ,  H04R2420/01 ,  H04R2430/03

摘要： In accordance with embodiments of the present disclosure, a processing system may include multiple selectable processing paths for processing an analog signal in order to reduce noise and increase dynamic range. Techniques are employed to transition between processing paths and calibrate operational parameters of the two paths in order to reduce or eliminate artifacts caused by switching between processing paths.

公开(公告)号：US09748971B2

公开(公告)日：2017-08-29

申请号：US15243305

申请日：2016-08-22

申请人： Cirrus Logic International Semiconductor Ltd.

发明人： John Paul Lesso ,  Emmanuel Philippe Christian Hardy

IPC分类号： H03M7/30 ,  H03M1/18 ,  H03M1/50 ,  H03M3/00 ,  H03K7/08 ,  H03K9/08

CPC分类号： H03M7/30 ,  H03K7/08 ,  H03K9/08 ,  H03M1/18 ,  H03M1/181 ,  H03M1/50 ,  H03M1/504 ,  H03M3/484 ,  H03M2201/00

摘要： This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).

公开(公告)号：US09525940B1

公开(公告)日：2016-12-20

申请号：US14476507

申请日：2014-09-03

申请人： Cirrus Logic, Inc.

发明人： Edmund Mark Schneider ,  Aniruddha Satoskar ,  Daniel J. Allen ,  Seyedeh Maryam Mortazavi Zanjani

IPC分类号： H04B15/00 ,  H04R3/02 ,  H03M1/00 ,  H03M1/06 ,  H03M1/18 ,  H03M3/00

CPC分类号： H04R3/02 ,  H03M1/002 ,  H03M1/0631 ,  H03M1/18 ,  H03M1/181 ,  H03M1/188 ,  H03M3/466 ,  H04R3/04 ,  H04R2420/01 ,  H04R2430/03

摘要： In accordance with embodiments of the present disclosure, a processing system may include multiple selectable processing paths for processing an analog signal in order to reduce noise and increase dynamic range. Techniques are employed to transition between processing paths and calibrate operational parameters of the two paths in order to reduce or eliminate artifacts caused by switching between processing paths.

摘要翻译： 根据本公开的实施例，处理系统可以包括用于处理模拟信号的多个可选择的处理路径，以便降低噪声并增加动态范围。 采用技术来在处理路径之间转换并且校准两个路径的操作参数，以便减少或消除由处理路径之间的切换引起的伪影。

公开(公告)号：US09425813B2

公开(公告)日：2016-08-23

申请号：US14931332

申请日：2015-11-03

申请人： Cirrus Logic International Semiconductor Ltd.

发明人： John Paul Lesso ,  Emmanuel Philippe Christian Hardy

IPC分类号： H03M1/18 ,  H03M1/50 ,  H03M3/00

CPC分类号： H03M7/30 ,  H03K7/08 ,  H03K9/08 ,  H03M1/18 ,  H03M1/181 ,  H03M1/50 ,  H03M1/504 ,  H03M3/484 ,  H03M2201/00

摘要： This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).

摘要翻译： 本申请涉及模拟 - 数字转换器（ADC）。 ADC200具有第一转换器（201），用于接收模拟输入信号（AIN），并输出诸如脉冲宽度调制（PWM）信号的时间编码信号（DT），其基于输入信号和第一转换 增益设置（GIN）。 在一些实施例中，第一转换器具有用于产生PWM信号的PWM调制器（401），使得输入信号由可在时间上连续变化的脉冲宽度编码。 第二转换器（202）接收时间编码信号并基于时间编码信号（DT）和第二转换增益设置（GO）输出数字输出信号（DOUT）。 第二转换器可以具有第一PWM到数字调制器（403）。 增益分配块（204）基于时间编码信号（DT）生成第一和第二转换增益设置。 增益分配块（204）可以具有第二PWM到数字调制器（203），其可以具有第一PWM到数字调制器（403）的较低等待时间和/或更低的分辨率。

公开(公告)号：US08754797B2

公开(公告)日：2014-06-17

申请号：US13599539

申请日：2012-08-30

申请人： Venugopal Gopinathan ,  Udayan Dasgupta ,  Ganesan Thiagarajan

发明人： Venugopal Gopinathan ,  Udayan Dasgupta ,  Ganesan Thiagarajan

IPC分类号： H03M1/12 ,  H03M1/10

CPC分类号： H03M1/12 ,  H03M1/10 ,  H03M1/125 ,  H03M1/126 ,  H03M1/127 ,  H03M1/18 ,  H03M1/181

摘要： An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal.

摘要翻译： 提供了一种装置。 比较电路被配置为接收模拟信号。 参考电路耦合到比较电路，并被配置为向比较电路提供多个参考信号。 A转换电路耦合到比较电路，并被配置为检测比较电路的输出的变化。 时间数字转换器（TDC）耦合到比较电路。 定时器耦合到比较电路。 速率控制电路耦合到转换电路。 输出电路耦合到速率控制电路和TDC，其中输出电路被配置为输出模拟信号的同步数字表示和模拟信号的异步数字表示中的至少一个。

公开(公告)号：US08749411B2

公开(公告)日：2014-06-10

申请号：US13746312

申请日：2013-01-22

申请人： Yen-Chien Cheng ,  Yung-Chi Yang ,  Chien-Yi Wu

发明人： Yen-Chien Cheng ,  Yung-Chi Yang ,  Chien-Yi Wu

IPC分类号： H03M1/06

CPC分类号： H03M1/1235 ,  H03M1/181

摘要： An analog-to-digital conversion device and a method thereof are provided. The analog-to-digital conversion device includes a first level adjustment unit, an analog-to-digital converter (ADC), and a linear range detection unit. The ADC converts a test signal or a first input signal to generate a test data stream or a first output data stream. In an adjustment mode, the linear range detection unit obtains a conversion curve of the ADC by using the test data stream and determines whether to adjust offset control information according to a linear range of the conversion curve. In an operation mode, the linear range detection unit continues outputting the offset control information. Additionally, before transmitting the first input signal, the first level adjustment unit adjusts a direct-current level of the first input signal according to the offset control information to allow the first input signal to be within the linear range of the conversion curve.

摘要翻译： 提供了一种模拟 - 数字转换装置及其方法。 模数转换装置包括第一电平调整单元，模数转换器（ADC）和线性范围检测单元。 ADC转换测试信号或第一输入信号以产生测试数据流或第一输出数据流。 在调整模式中，线性范围检测单元通过使用测试数据流来获得ADC的转换曲线，并根据转换曲线的线性范围来确定是否调整偏移控制信息。 在操作模式中，线性范围检测单元继续输出偏移控制信息。 此外，在发送第一输入信号之前，第一电平调整单元根据偏移控制信息来调整第一输入信号的直流电平，以允许第一输入信号在转换曲线的线性范围内。

公开(公告)号：US08483343B2

公开(公告)日：2013-07-09

申请号：US12056084

申请日：2008-03-26

申请人： Oscar E. Agazzi ,  Diego E. Crivelli ,  Hugo S. Carrer ,  Mario R. Hueda ,  German C. Luna ,  Carl Grace

发明人： Oscar E. Agazzi ,  Diego E. Crivelli ,  Hugo S. Carrer ,  Mario R. Hueda ,  German C. Luna ,  Carl Grace

IPC分类号： H04L7/00

CPC分类号： H04L7/0083 ,  H03M1/0626 ,  H03M1/0692 ,  H03M1/0695 ,  H03M1/1042 ,  H03M1/1215 ,  H03M1/181 ,  H03M1/42 ,  H03M1/44 ,  H04L7/0004 ,  H04L7/0062 ,  H04L7/0087 ,  H04L25/0204 ,  H04L25/03038

摘要： A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

摘要翻译： 接收机（例如，用于10G光纤通信链路）包括耦合到多通道均衡器的交错ADC，其可以为交错ADC内的不同ADC通道提供不同的均衡。 也就是说，多通道均衡器可以补偿信道相关的损伤。 在一种方法中，多信道均衡器是耦合到维特比解码器（例如滑块维特比解码器（SBVD））的前馈均衡器（FFE）; 并且使用LMS算法适配维特比解码器的FFE和/或信道估计器。

公开(公告)号：US20130154862A1

公开(公告)日：2013-06-20

申请号：US13767407

申请日：2013-02-14

申请人： Rosemount Inc.

发明人： Jason H. Rud ,  Andrew J. Bronczyk

IPC分类号： H03M1/20

CPC分类号： H03M1/20 ,  H03M1/1235 ,  H03M1/181

摘要： A process variable transmitter is used to measure a process variable, and, in doing so, dynamically changes the resolution of the A/D converter based upon the measured value of the analog input signal. This can be done by automatically adjusting the configurable resolution gain adjustment based on the value of the analog signal being measured, by normalizing the input signal being measured so that it is centered in an optimal resolution window of the A/D converter, or by adjusting a voltage reference provided to the A/D converter.

摘要翻译： 过程变量发送器用于测量过程变量，并且在这样做时，基于模拟输入信号的测量值来动态地改变A / D转换器的分辨率。 这可以通过基于所测量的模拟信号的值自动调整可配置的分辨率增益调整，通过对所测量的输入信号进行归一化，使其在A / D转换器的最佳分辨率窗口中居中，或者通过调整 提供给A / D转换器的电压参​​考。