公开(公告)号：US20240385842A1

公开(公告)日：2024-11-21

申请号：US18774678

申请日：2024-07-16

Applicant: Apple Inc.

Inventor： Ian D Kountanis ,  Douglas C Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru ,  Ethan R Schuchman ,  Niket K Choudhary ,  Kulin N Kothari ,  Haoyan Jia

IPC: G06F9/38

Abstract: A processor may include a bias prediction circuit and an instruction prediction circuit to provide respective predictions for a conditional instruction. The bias prediction circuit may provide a bias prediction whether a condition of the conditional instruction is biased true or biased false. The instruction prediction circuit may provide an instruction prediction whether the condition of the conditional instruction is true of false. Responsive to a bias prediction that the condition of the conditional instruction is biased true or biased false, the processor may use the bias prediction from the bias prediction circuit to speculatively process the conditional instruction. Otherwise, the processor may use the instruction prediction from the instruction prediction circuit to speculatively process the conditional instruction.

公开(公告)号：US20250036416A1

公开(公告)日：2025-01-30

申请号：US18358894

申请日：2023-07-25

Applicant: Apple Inc.

Inventor： Muawya M Al-Otoom ,  Pruthivi Vuyyuru ,  Andrew H Lin ,  Ian D Kountanis

IPC: G06F9/38 ,  G06F12/0875

Abstract: A processor may include an indirect control transfer prediction circuit. During fetch of an indirect control transfer instruction from memory to an instruction cache of the processor, the indirect control transfer prediction circuit may predict whether the indirect control transfer instruction is biased. Responsive to a prediction that the indirect control transfer instruction is biased, the indirect control transfer prediction circuit may cause the indirect control transfer instruction to be executed as an unconditional direct control transfer instruction according to the predicted bias.

公开(公告)号：US20230244494A1

公开(公告)日：2023-08-03

申请号：US17590719

申请日：2022-02-01

Applicant: Apple Inc.

Inventor： Ian D Kountanis ,  Douglas C Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru ,  Ethan R Schuchman ,  Niket K Choudhary ,  Kulin N Kothari ,  Haoyan Jia

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/3806 ,  G06F9/30196 ,  G06F9/30058

Abstract: A processor may include a bias prediction circuit and an instruction prediction circuit to provide respective predictions for a conditional instruction. The bias prediction circuit may provide a bias prediction whether a condition of the conditional instruction is biased true or biased false. The instruction prediction circuit may provide an instruction prediction whether the condition of the conditional instruction is true of false. Responsive to a bias prediction that the condition of the conditional instruction is biased true or biased false, the processor may use the bias prediction from the bias prediction circuit to speculatively process the conditional instruction. Otherwise, the processor may use the instruction prediction from the instruction prediction circuit to speculatively process the conditional instruction.

公开(公告)号：US12067399B2

公开(公告)日：2024-08-20

申请号：US17590719

申请日：2022-02-01

Applicant: Apple Inc.

Inventor： Ian D Kountanis ,  Douglas C Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru ,  Ethan R Schuchman ,  Niket K Choudhary ,  Kulin N Kothari ,  Haoyan Jia

IPC: G06F9/38

CPC classification number: G06F9/3848 ,  G06F9/3806 ,  G06F9/3844

Abstract: A processor may include a bias prediction circuit and an instruction prediction circuit to provide respective predictions for a conditional instruction. The bias prediction circuit may provide a bias prediction whether a condition of the conditional instruction is biased true or biased false. The instruction prediction circuit may provide an instruction prediction whether the condition of the conditional instruction is true of false. Responsive to a bias prediction that the condition of the conditional instruction is biased true or biased false, the processor may use the bias prediction from the bias prediction circuit to speculatively process the conditional instruction. Otherwise, the processor may use the instruction prediction from the instruction prediction circuit to speculatively process the conditional instruction.

公开(公告)号：US11809874B2

公开(公告)日：2023-11-07

申请号：US17590722

申请日：2022-02-01

Applicant: Apple Inc.

Inventor： Ethan R Schuchman ,  Niket K Choudhary ,  Kulin N Kothari ,  Haoyan Jia ,  Ian D Kountanis ,  Douglas C Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/30058 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3885

Abstract: A processor may include an instruction distribution circuit and a plurality of execution pipelines. The instruction distribution circuit may distribute a conditional instruction to a first execution pipeline for execution when the conditional instruction is associated with a prediction of a high confidence level, or to a second execution pipeline for execution when the conditional instruction is associated with a prediction of a low confidence level. The second execution pipeline, not the first execution pipeline, may directly instruct the processor to obtain an instruction from a target address for execution, when the conditional instruction is mispredicted. Thus, when the conditional instruction is distributed to the first execution pipeline for execution and determined to be mispredicted, the first execution pipeline may cause the conditional instruction to be re-executed in the second execution pipeline to cause the instruction from the correct target address to be obtained for execution.

公开(公告)号：US10241557B2

公开(公告)日：2019-03-26

申请号：US14104042

申请日：2013-12-12

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Ronald P Hall ,  Ramesh B Gunna ,  Ian D Kountanis ,  Shyam Sundar ,  André Seznec

IPC: G06F9/38 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3296

Abstract: A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.