公开(公告)号：US10241557B2

公开(公告)日：2019-03-26

申请号：US14104042

申请日：2013-12-12

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Ronald P Hall ,  Ramesh B Gunna ,  Ian D Kountanis ,  Shyam Sundar ,  André Seznec

IPC: G06F9/38 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3296

Abstract: A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.

公开(公告)号：US20190286218A1

公开(公告)日：2019-09-19

申请号：US16363517

申请日：2019-03-25

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Ronald P. Hall ,  Ramesh B. Gunna ,  Ian D. Kountanis ,  Shyam Sundar ,  André Seznec

IPC: G06F1/3237 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/324 ,  G06F9/38

Abstract: A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.

公开(公告)号：US10901484B2

公开(公告)日：2021-01-26

申请号：US16363517

申请日：2019-03-25

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Ronald P. Hall ,  Ramesh B. Gunna ,  Ian D. Kountanis ,  Shyam Sundar ,  André Seznec

IPC: G06F9/38 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3296

Abstract: A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.

公开(公告)号：US20150169041A1

公开(公告)日：2015-06-18

申请号：US14104042

申请日：2013-12-12

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Ronald P. Hall ,  Ramesh B. Gunna ,  Ian D. Kountanis ,  Shyam Sundar ,  André Seznec

IPC: G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/3802 ,  G06F9/3806 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/172

Abstract: A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.

Abstract translation: 处理器包括用于禁用分支预测单元的存储器阵列的机构。 处理器可以包括可以包括多个条目的下一个提取预测单元。 每个条目可以对应于下一个指令获取组，并且可以存储对应的下一个提取组是否包括条件分支指令的指示。 响应于下一个提取组不包括条件分支指令的指示，获取预测单元可以被配置为在下一个指令执行周期中禁止分支预测单元的存储器阵列。