公开(公告)号：US20240320776A1

公开(公告)日：2024-09-26

申请号：US18125046

申请日：2023-03-22

Applicant: Apple Inc.

Inventor： Hoi Man S. Ng ,  Oren Kerem ,  Wayne Eric Burk ,  Michael Bekerman ,  Marc A Schaub

IPC: G06T1/20

CPC classification number: G06T1/20

Abstract: Embodiments relate to generating a Quality of Service (QOS) parameter indicating latency tolerance of an image signal processor by determining and processing latency tolerance values of its individual pipeline circuits. At least a subset of the pipeline circuits that performs image processing functions generates their individual latency tolerance values. Each of the individual latency tolerance value is determined as a difference between a sampling time at which an operation is performed on certain pixel data and a latest time by which the operation should be performed on the same pixel data. The individual latency tolerance values generated in this manner provides a mechanism to determine the QoS parameter relevant to an image signal processing scheme that involves access to memory multiple times to save and retrieve intermediate pixel data and process incoming pixel data in a real-time manner.

公开(公告)号：US11829237B1

公开(公告)日：2023-11-28

申请号：US17193730

申请日：2021-03-05

Applicant: Apple Inc.

Inventor： Marc A Schaub ,  Roy G. Moss ,  Michael Bekerman

IPC: G06F11/00 ,  H03M13/00 ,  G06F11/07 ,  G06F13/28

CPC classification number: G06F11/0793 ,  G06F13/28

Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.

公开(公告)号：US20230298124A1

公开(公告)日：2023-09-21

申请号：US17694670

申请日：2022-03-15

Applicant: Apple Inc.

Inventor： Ashwin S. Subramanian ,  Damon W Finney ,  Marc A Schaub ,  Albert C Kuo ,  Paul S Serris ,  Richard L Schober

IPC: G06T1/20 ,  G06T1/60 ,  G06F13/28 ,  H04N19/152 ,  H04N19/176

CPC classification number: G06T1/20 ,  G06F13/28 ,  G06T1/60 ,  H04N19/152 ,  H04N19/176

Abstract: Embodiments relate to an image signal processor that includes an image processing circuit, a buffer, and a rate limiter circuit. The image processing circuit perform operations associated with image signal processing. The buffer stores the image data provided by the system memory. The buffer includes a shared that is dynamically allocated among the image processing circuits. The rate limiter circuit arbitrates allocation of the shared section. The arbitration process includes allocating data credits for the shared section to an image processing circuit. The rate limiter circuit determines a first number of blocks in the shared section that are allocated for pending requests and a second number of blocks that include data pending to be consumed by the image processing circuit. If the total allocated blocks occupied by the image processing circuit exceed a throttling threshold, the image processing circuit will be throttled by an exponential factor.