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    Error Detection and Recovery When Streaming Data
    1.
    发明公开
    Error Detection and Recovery When Streaming Data 审中-公开

    公开(公告)号：US20240232000A9

    公开(公告)日：2024-07-11

    申请号：US18490675

    申请日：2023-10-19

    Applicant: Apple Inc.

    Inventor： Marc A. Schaub ,  Roy G. Moss ,  Michael Bekerman

    IPC: G06F11/07 ,  G06F13/28

    CPC classification number: G06F11/0793 ,  G06F13/28

    Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.

    Error Detection and Recovery When Streaming Data
    3.
    发明公开
    Error Detection and Recovery When Streaming Data 审中-公开

    公开(公告)号：US20240134737A1

    公开(公告)日：2024-04-25

    申请号：US18490675

    申请日：2023-10-18

    Applicant: Apple Inc.

    Inventor： Marc A. Schaub ,  Roy G. Moss ,  Michael Bekerman

    IPC: G06F11/07 ,  G06F13/28

    CPC classification number: G06F11/0793 ,  G06F13/28

    Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.

    Precise Time Management for Peripheral Device Using Local Time Base
    6.
    发明申请
    Precise Time Management for Peripheral Device Using Local Time Base 有权

    公开(公告)号：US20230091434A1

    公开(公告)日：2023-03-23

    申请号：US17482178

    申请日：2021-09-22

    Applicant: Apple Inc.

    Inventor： Christopher D. Finan ,  Alexander Ukanwa ,  Charles F. Dominguez ,  Kalpana Bansal ,  Michael Bekerman ,  Remi Clavel

    IPC: G06F1/06 ,  G06F13/42

    Abstract: An apparatus for time management of a peripheral device is disclosed. A peripheral interface circuit receives information from a host circuit over a peripheral bus, the host circuit maintaining a global timebase in accordance with a first clock signal within a first clock domain. The peripheral interface circuit maintains, based om a second clock signal within a second clock domain, a first local timebase correlated to the global timebase. A peripheral control circuit operates in a third clock domain and maintains a second local timebase based on the first. The peripheral interface circuit determines phase and frequency differences between the second and third clock signals in determining a correlation between the second and first local timebases. A peripheral logic circuit in the third clock domain performs, operations that utilize a timestamp from the second local timebase, which accounts for correlation with the first local timebase.

    QUALITY OF SERVICE CONTROL SCHEME FOR ACCESS TO MEMORY BY IMAGE SIGNAL PROCESSOR
    7.
    发明公开
    QUALITY OF SERVICE CONTROL SCHEME FOR ACCESS TO MEMORY BY IMAGE SIGNAL PROCESSOR 审中-公开

    公开(公告)号：US20240320776A1

    公开(公告)日：2024-09-26

    申请号：US18125046

    申请日：2023-03-22

    Applicant: Apple Inc.

    Inventor： Hoi Man S. Ng ,  Oren Kerem ,  Wayne Eric Burk ,  Michael Bekerman ,  Marc A Schaub

    IPC: G06T1/20

    CPC classification number: G06T1/20

    Abstract: Embodiments relate to generating a Quality of Service (QOS) parameter indicating latency tolerance of an image signal processor by determining and processing latency tolerance values of its individual pipeline circuits. At least a subset of the pipeline circuits that performs image processing functions generates their individual latency tolerance values. Each of the individual latency tolerance value is determined as a difference between a sampling time at which an operation is performed on certain pixel data and a latest time by which the operation should be performed on the same pixel data. The individual latency tolerance values generated in this manner provides a mechanism to determine the QoS parameter relevant to an image signal processing scheme that involves access to memory multiple times to save and retrieve intermediate pixel data and process incoming pixel data in a real-time manner.

    Precise time management for peripheral device using local time base
    10.
    发明授权
    Precise time management for peripheral device using local time base 有权

    公开(公告)号：US11687115B2

    公开(公告)日：2023-06-27

    申请号：US17482178

    申请日：2021-09-22

    Applicant: Apple Inc.

    Inventor： Christopher D. Finan ,  Alexander Ukanwa ,  Charles F. Dominguez ,  Kalpana Bansal ,  Michael Bekerman ,  Remi Clavel

    IPC: G06F1/06 ,  G06F13/42

    CPC classification number: G06F1/06 ,  G06F13/423

    Abstract: An apparatus for time management of a peripheral device is disclosed. A peripheral interface circuit receives information from a host circuit over a peripheral bus, the host circuit maintaining a global timebase in accordance with a first clock signal within a first clock domain. The peripheral interface circuit maintains, based om a second clock signal within a second clock domain, a first local timebase correlated to the global timebase. A peripheral control circuit operates in a third clock domain and maintains a second local timebase based on the first. The peripheral interface circuit determines phase and frequency differences between the second and third clock signals in determining a correlation between the second and first local timebases. A peripheral logic circuit in the third clock domain performs, operations that utilize a timestamp from the second local timebase, which accounts for correlation with the first local timebase.

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