公开(公告)号：US20220084474A1

公开(公告)日：2022-03-17

申请号：US17368522

申请日：2021-07-06

Applicant: Apple Inc.

Inventor： Prabhu Rajamani ,  Liang Deng ,  Oren Kerem ,  Meir Harar ,  Ido Yaacov Soffair ,  Assaf Menachem ,  John H. Kelm ,  Rohit K. Gupta

IPC: G09G3/34

Abstract: Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.

公开(公告)号：US11024006B2

公开(公告)日：2021-06-01

申请号：US16391224

申请日：2019-04-22

Applicant: Apple Inc.

Inventor： Maxim Smirnov ,  Elena Lamburn ,  Oren Kerem ,  Chihsin Wu

IPC: G06T3/40 ,  G06T3/00 ,  G06T5/30 ,  G06T5/50 ,  G06T5/00

Abstract: A portable electronic device may include an image signal processor that includes a clipping circuit, a pyramid generator circuit, and an image fusion processor. The clipping circuit clips pixel values that are under-exposed or over-exposed. The pyramid generator circuit applies a filter to the pixels of the image to generate a filtered image. Some of the filtered pixels may be generated from one or more clipped pixel values. The pyramid generator circuit identifies those filtered pixels that are generated from one or more clipped pixel values and marks the identified filtered pixels with a tag. The pyramid generator circuit decimates the filtered image to generate a downscaled image, which may include one or more filtered pixels that are marked with the tags. The image fusion processor fuses the downscaled image with another image. The pixels that are marked with the tags may be disregarded in the fusion process.

公开(公告)号：US20240305911A1

公开(公告)日：2024-09-12

申请号：US18120208

申请日：2023-03-10

Applicant: Apple Inc.

Inventor： Wayne Eric Burk ,  Oren Kerem ,  Hoi Man S. Ng ,  Michael Bekerman

IPC: H04N25/76 ,  H04N17/00 ,  H04N23/95 ,  H04N25/703

CPC classification number: H04N25/7795 ,  H04N17/002 ,  H04N23/95 ,  H04N25/703

Abstract: Embodiments relate to detecting a timeout error on receipt of valid pixel data from an image sensor by a sensor interface circuit. When the valid pixel data is not timely received at the sensor interface circuit, a timeout error signal is generated by the sensor interface circuit. A time limit for determining the timeout error signal may be defined by a global clock that provides a clock signal to the sensor interface circuit and other circuits. As a result, the sensor interface circuit generates a dummy frame and sends out the dummy frame to subsequent circuits so that the timeout error does not bottleneck subsequent processing stages. In contrast, if the valid pixel data is timely received, sensor data received from the image sensor is unpacked into a frame of pixels.

公开(公告)号：US11010870B2

公开(公告)日：2021-05-18

申请号：US16848287

申请日：2020-04-14

Applicant: Apple Inc.

Inventor： Maxim W. Smirnov ,  David R. Pope ,  Oren Kerem ,  Elena Lamburn

IPC: G06T3/40 ,  G06T5/00 ,  G06T7/90 ,  G06T5/20

Abstract: Embodiments relate to two stage multi-scale processing of an image. A first stage processing circuitry generates an unscaled single color version of the image that undergoes noise reduction before generating a high frequency component of the unscaled single color version. A scaler generates a first downscaled version of the image comprising a plurality of color components. A second stage processing circuitry generates a plurality of sequentially downscaled images based on the first downscaled version. The second stage processing circuitry processes the first downscaled version and the downscaled images to generate a processed version of the first downscaled version. The unscaled single color high frequency component and the processed version of the first downscaled version of the image are merged to generate a processed version of the image.

公开(公告)号：US11842700B2

公开(公告)日：2023-12-12

申请号：US18109691

申请日：2023-02-14

Applicant: Apple Inc.

Inventor： Prabhu Rajamani ,  Liang Deng ,  Oren Kerem ,  Meir Harar ,  Ido Yaacov Soffair ,  Assaf Menachem ,  John H. Kelm ,  Rohit K. Gupta

IPC: G09G3/34

CPC classification number: G09G3/3426 ,  G09G2320/0233 ,  G09G2320/0646 ,  G09G2330/021 ,  G09G2360/18

Abstract: Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.

公开(公告)号：US10657623B2

公开(公告)日：2020-05-19

申请号：US16100823

申请日：2018-08-10

Applicant: Apple Inc.

Inventor： Maxim Smirnov ,  David R. Pope ,  Oren Kerem ,  Elena Lamburn

IPC: G06T3/40 ,  G06T5/00 ,  G06T7/90 ,  G06T5/20

Abstract: Embodiments relate to two stage multi-scale processing of an image. A first stage processing circuitry generates an unscaled single color version of the image that undergoes noise reduction before generating a high frequency component of the unscaled single color version. A scaler generates a first downscaled version of the image comprising a plurality of color components. A second stage processing circuitry generates a plurality of sequentially downscaled images based on the first downscaled version. The second stage processing circuitry processes the first downscaled version and the downscaled images to generate a processed version of the first downscaled version. The unscaled single color high frequency component and the processed version of the first downscaled version of the image are merged to generate a processed version of the image.

公开(公告)号：US20240320776A1

公开(公告)日：2024-09-26

申请号：US18125046

申请日：2023-03-22

Applicant: Apple Inc.

Inventor： Hoi Man S. Ng ,  Oren Kerem ,  Wayne Eric Burk ,  Michael Bekerman ,  Marc A Schaub

IPC: G06T1/20

CPC classification number: G06T1/20

Abstract: Embodiments relate to generating a Quality of Service (QOS) parameter indicating latency tolerance of an image signal processor by determining and processing latency tolerance values of its individual pipeline circuits. At least a subset of the pipeline circuits that performs image processing functions generates their individual latency tolerance values. Each of the individual latency tolerance value is determined as a difference between a sampling time at which an operation is performed on certain pixel data and a latest time by which the operation should be performed on the same pixel data. The individual latency tolerance values generated in this manner provides a mechanism to determine the QoS parameter relevant to an image signal processing scheme that involves access to memory multiple times to save and retrieve intermediate pixel data and process incoming pixel data in a real-time manner.

公开(公告)号：US12081892B1

公开(公告)日：2024-09-03

申请号：US18120208

申请日：2023-03-10

Applicant: Apple Inc.

Inventor： Wayne Eric Burk ,  Oren Kerem ,  Hoi Man S. Ng ,  Michael Bekerman

IPC: H04N25/76 ,  H04N17/00 ,  H04N23/95 ,  H04N25/703

CPC classification number: H04N25/7795 ,  H04N17/002 ,  H04N23/95 ,  H04N25/703

Abstract: Embodiments relate to detecting a timeout error on receipt of valid pixel data from an image sensor by a sensor interface circuit. When the valid pixel data is not timely received at the sensor interface circuit, a timeout error signal is generated by the sensor interface circuit. A time limit for determining the timeout error signal may be defined by a global clock that provides a clock signal to the sensor interface circuit and other circuits. As a result, the sensor interface circuit generates a dummy frame and sends out the dummy frame to subsequent circuits so that the timeout error does not bottleneck subsequent processing stages. In contrast, if the valid pixel data is timely received, sensor data received from the image sensor is unpacked into a frame of pixels.

公开(公告)号：US20200334787A1

公开(公告)日：2020-10-22

申请号：US16391224

申请日：2019-04-22

Applicant: Apple Inc.

Inventor： Maxim Smirnov ,  Elena Lamburn ,  Oren Kerem ,  Chihsin Wu

IPC: G06T3/40 ,  G06T3/00 ,  G06T5/30 ,  G06T5/00 ,  G06T5/50

Abstract: A portable electronic device may include an image signal processor that includes a clipping circuit, a pyramid generator circuit, and an image fusion processor. The clipping circuit clips pixel values that are under-exposed or over-exposed. The pyramid generator circuit applies a filter to the pixels of the image to generate a filtered image. Some of the filtered pixels may be generated from one or more clipped pixel values. The pyramid generator circuit identifies those filtered pixels that are generated from one or more clipped pixel values and marks the identified filtered pixels with a tag. The pyramid generator circuit decimates the filtered image to generate a downscaled image, which may include one or more filtered pixels that are marked with the tags. The image fusion processor fuses the downscaled image with another image. The pixels that are marked with the tags may be disregarded in the fusion process.

公开(公告)号：US20230197022A1

公开(公告)日：2023-06-22

申请号：US18109691

申请日：2023-02-14

Applicant: Apple Inc.

Inventor： Prabhu Rajamani ,  Liang Deng ,  Oren Kerem ,  Meir Harar ,  Ido Yaacov Soffair ,  Assaf Menachem ,  John H. Kelm ,  Rohit K. Gupta

IPC: G09G3/34

CPC classification number: G09G3/3426 ,  G09G2320/0646 ,  G09G2360/18 ,  G09G2320/0233 ,  G09G2330/021

Abstract: Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.