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公开(公告)号：US20220270567A1
公开(公告)日：2022-08-25
申请号：US17742251
申请日：2022-05-11
Applicant: Apple Inc.
Inventor： Jim C. Chou , Honkai Tam , Roy G. Moss , Arthur L. Spence
Abstract: An electronic device includes a display panel and image processing circuitry. The image processing circuitry receives input image data corresponding to an image to display on the display panel, modifies the input image data by executing a first context task (e.g., lower priority task), and receives a context switch request. The image processing circuitry also pauses modification of the input image data by pausing execution of the first context task and then switches to modifying the input image data by executing a second context task (e.g., higher priority task).
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公开(公告)号：US12111721B2
公开(公告)日：2024-10-08
申请号：US18490675
申请日：2023-10-19
Applicant: Apple Inc.
Inventor： Marc A. Schaub , Roy G. Moss , Michael Bekerman
CPC classification number: G06F11/0793 , G06F13/28
Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.
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公开(公告)号：US20240264963A1
公开(公告)日：2024-08-08
申请号：US18637305
申请日：2024-04-16
Applicant: Apple Inc.
Inventor： Marc A. Schaub , Roy G. Moss
CPC classification number: G06F13/37 , G06F9/30069 , G06F9/5022 , G06F9/544 , G06F13/1642 , G06F13/28
Abstract: Systems, apparatuses, and methods for performing scatter and gather direct memory access (DMA) streaming through a circular buffer are described. A system includes a circular buffer, producer DMA engine, and consumer DMA engine. After the producer DMA engine writes or skips over a given data chunk of a first frame to the buffer, the producer DMA engine sends an updated write pointer to the consumer DMA engine indicating that a data credit has been committed to the buffer and that the data credit is ready to be consumed. After the consumer DMA engine reads or skips over the given data chunk of the first frame from the buffer, the consumer DMA engine sends an updated read pointer to the producer DMA engine indicating that the data credit has been consumed and that space has been freed up in the buffer to be reused by the producer DMA engine.
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公开(公告)号：US11829237B1
公开(公告)日：2023-11-28
申请号：US17193730
申请日：2021-03-05
Applicant: Apple Inc.
Inventor： Marc A Schaub , Roy G. Moss , Michael Bekerman
CPC classification number: G06F11/0793 , G06F13/28
Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.
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公开(公告)号：US20240134737A1
公开(公告)日：2024-04-25
申请号：US18490675
申请日：2023-10-18
Applicant: Apple Inc.
Inventor： Marc A. Schaub , Roy G. Moss , Michael Bekerman
CPC classification number: G06F11/0793 , G06F13/28
Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.
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Patent Agency Ranking
公开(公告)号：US11335296B2
公开(公告)日：2022-05-17
申请号：US17020710
申请日：2020-09-14
Applicant: Apple Inc.
Inventor： Jim C. Chou , Honkai Tam , Roy G. Moss , Arthur L. Spence
Abstract: An electronic device includes a display panel and image processing circuitry. The image processing circuitry receives input image data corresponding to an image to display on the display panel, modifies the input image data by executing a first context task (e.g., lower priority task), and receives a context switch request. The image processing circuitry also pauses modification of the input image data by pausing execution of the first context task and then switches to modifying the input image data by executing a second context task (e.g., higher priority task).
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公开(公告)号：US20220084482A1
公开(公告)日：2022-03-17
申请号：US17020710
申请日：2020-09-14
Applicant: Apple Inc.
Inventor： Jim C. Chou , Honkai Tam , Roy G. Moss , Arthur L. Spence
Abstract: An electronic device includes a display panel and image processing circuitry. The image processing circuitry receives input image data corresponding to an image to display on the display panel, modifies the input image data by executing a first context task (e.g., lower priority task), and receives a context switch request. The image processing circuitry also pauses modification of the input image data by pausing execution of the first context task and then switches to modifying the input image data by executing a second context task (e.g., higher priority task).
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公开(公告)号：US20240232000A9
公开(公告)日：2024-07-11
申请号：US18490675
申请日：2023-10-19
Applicant: Apple Inc.
Inventor： Marc A. Schaub , Roy G. Moss , Michael Bekerman
CPC classification number: G06F11/0793 , G06F13/28
Abstract: Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.
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公开(公告)号：US12001365B2
公开(公告)日：2024-06-04
申请号：US16922623
申请日：2020-07-07
Applicant: Apple Inc.
Inventor： Marc A. Schaub , Roy G. Moss
CPC classification number: G06F13/37 , G06F9/30069 , G06F9/5022 , G06F9/544 , G06F13/1642 , G06F13/28
Abstract: Systems, apparatuses, and methods for performing scatter and gather direct memory access (DMA) streaming through a circular buffer are described. A system includes a circular buffer, producer DMA engine, and consumer DMA engine. After the producer DMA engine writes or skips over a given data chunk of a first frame to the buffer, the producer DMA engine sends an updated write pointer to the consumer DMA engine indicating that a data credit has been committed to the buffer and that the data credit is ready to be consumed. After the consumer DMA engine reads or skips over the given data chunk of the first frame from the buffer, the consumer DMA engine sends an updated read pointer to the producer DMA engine indicating that the data credit has been consumed and that space has been freed up in the buffer to be reused by the producer DMA engine.
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公开(公告)号：US11756503B2
公开(公告)日：2023-09-12
申请号：US17742251
申请日：2022-05-11
Applicant: Apple Inc.
Inventor： Jim C. Chou , Honkai Tam , Roy G. Moss , Arthur L. Spence
CPC classification number: G09G5/003 , G06F3/1407 , G06F3/147 , G06T11/60 , G09G2310/02 , G09G2360/18
Abstract: An electronic device includes a display panel and image processing circuitry. The image processing circuitry receives input image data corresponding to an image to display on the display panel, modifies the input image data by executing a first context task (e.g., lower priority task), and receives a context switch request. The image processing circuitry also pauses modification of the input image data by pausing execution of the first context task and then switches to modifying the input image data by executing a second context task (e.g., higher priority task).
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