Method of selective power cycling of components in a memory device independently by turning off power to a memory array or memory controller
    1.
    发明授权
    Method of selective power cycling of components in a memory device independently by turning off power to a memory array or memory controller 有权
    通过关闭存储器阵列或存储器控制器的电源来独立地选择性地对存储器件中的组件进行功率循环的方法

    公开(公告)号:US08612791B2

    公开(公告)日:2013-12-17

    申请号:US13918240

    申请日:2013-06-14

    Applicant: Apple Inc.

    CPC classification number: G06F1/3275 G06F1/3225 Y02D10/13 Y02D10/14

    Abstract: In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.

    Abstract translation: 在非易失性存储器系统中,物理上分离的电源轨从主机系统提供给NVM设备,用于独立地对NVM设备中的控制器和存储器阵列进行电力循环。 NVM设备的控制器可以通过主机通道向主机系统发送电源循环请求信号,或更新NVM设备中的状态寄存器。 主机系统接收并解码电源周期请求信号,或读取状态寄存器,并执行电源循环请求,其中可以包括对NVM设备中的控制器或存储器阵列进行电源循环,或两者兼而有之。 功率循环请求可以基于非易失性存储器系统的功率状态,其可以由控制器或主机系统管理,或两者兼而有之。

    Memory Array Power Cycling
    2.
    发明申请
    Memory Array Power Cycling 有权
    存储阵列电源循环

    公开(公告)号:US20130283081A1

    公开(公告)日:2013-10-24

    申请号:US13918240

    申请日:2013-06-14

    Applicant: Apple Inc.

    CPC classification number: G06F1/3275 G06F1/3225 Y02D10/13 Y02D10/14

    Abstract: In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.

    Abstract translation: 在非易失性存储器系统中,物理上分离的电源轨从主机系统提供给NVM设备,用于独立地对NVM设备中的控制器和存储器阵列进行电力循环。 NVM设备的控制器可以通过主机通道向主机系统发送电源循环请求信号,或更新NVM设备中的状态寄存器。 主机系统接收并解码电源周期请求信号,或读取状态寄存器,并执行电源循环请求,其中可以包括对NVM设备中的控制器或存储器阵列进行电源循环,或两者兼而有之。 功率循环请求可以基于非易失性存储器系统的功率状态,其可以由控制器或主机系统管理,或两者兼而有之。

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