公开(公告)号：US12124311B2

公开(公告)日：2024-10-22

申请号：US17533548

申请日：2021-11-23

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Vedula Venkata Srikant Bharadwaj

IPC分类号： G06F1/00 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3296

CPC分类号： G06F1/3225 ,  G06F1/324 ,  G06F1/3296

摘要： A processing unit includes compute units partitioned into one or islands that are provided with operating voltages and clock signals having clock frequencies independent of providing operating voltages or clock signals to other islands of compute units. The processing unit also includes dynamic voltage and frequency scaling (DVFS) hardware configured to compute one or more numbers of active memory barriers in the one or more islands. The DVFS hardware is also configured to modify the operating voltages or clock frequencies provided to the one or more islands in response to a change in numbers of active memory barriers in the one or more islands. In some cases, the operating voltage or clock frequency provided to an island is increased in response to the number of active memory barriers in the island decreasing. The operating voltage or clock frequency provided to the island is decreased in response to the number of active memory barriers in the island increasing.

公开(公告)号：US12079062B2

公开(公告)日：2024-09-03

申请号：US18048661

申请日：2022-10-21

申请人： Quanta Computer Inc.

发明人： Yung-Fu Li

IPC分类号： G06F1/32 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3203

CPC分类号： G06F1/3287 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3203

摘要： A system and method to save power in a computer system is disclosed. The system includes a power controller controlling connection of power to each of a plurality of memory components. A processor is coupled to the memory components. The processor operates with varying utilization levels of the memory components. A management controller is coupled to the processor and the power controller. The management controller determines a period of low utilization based on memory utilization data from the processor. The management controller commands the power controller to disable power to some of the plurality of memory components during the period of low utilization.

公开(公告)号：US20240288924A1

公开(公告)日：2024-08-29

申请号：US18443955

申请日：2024-02-16

申请人： Micron Technology, Inc.

发明人： Liang Yu ,  Jonathan S. Parry ,  Giuseppe Cariello

IPC分类号： G11C16/30

CPC分类号： G06F1/3225 ,  G06F11/3062

摘要： Methods, systems, and devices for power arbitration for systems of electronic components are described. A system may include a power source, a signaling conductor coupled with a voltage source, and a set of electronic components. One or more of the electronic components may include respective circuitry coupled with the power source and a respective switching component (e.g., a transistor) coupled with the signaling conductor. In some implementations, an electronic component of the set may be configured to determine an operation of its respective circuitry that is associated with a power consumption from the power source. Based on such a determination, the electronic component may switch its respective switching component in accordance with an identifier associated with the electronic component, and determine whether to perform the operation based on monitoring a signal level of the signaling conductor during the switching.

公开(公告)号：US12019497B2

公开(公告)日：2024-06-25

申请号：US17272055

申请日：2020-12-17

申请人： Micron Technology, Inc.

发明人： Tao Xiong ,  Guang Chang Ye ,  Jizhe Xing ,  Jun Shen

IPC分类号： G06F1/3234 ,  G06F1/3225 ,  G11C5/14

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  G11C5/14 ,  G11C2207/2227

摘要： Various embodiments described herein provide for a method for reduced power consumption by a memory system. A memory system of some embodiments monitors power state change requests received by the memory system from a host system, and determines a pattern of power state change requests received from the host system. Based on the determined pattern, the memory system can decide to activate or deactivate a reduced power consumption mode on the memory system. A reduced power consumption mode can comprise a first set of operation parameters that cause a memory system to operate with lower power consumption than a second set of operation parameters associated with a current operation mode, where the current operation mode is associated with a current power state set or last requested by the host system.

公开(公告)号：US20240192755A1

公开(公告)日：2024-06-13

申请号：US18077131

申请日：2022-12-07

申请人： Intel Corporation

发明人： Chuen Ming Tan ,  Venkataramani Gopalakrishnan ,  Aneesh Tuljapurkar ,  Vishwanath Somayaji ,  Tabassum Yasmin

IPC分类号： G06F1/3225 ,  G06F1/3287

CPC分类号： G06F1/3225 ,  G06F1/3287

摘要： Embodiments herein relate to a circuit which allows the re-use of an existing power supply units having main power rails and an auxiliary power rail, while supporting large memory configurations in a sleep state to avoid data loss. A processor determines whether a power requirement of memory modules in a computing device exceeds an available power of the auxiliary power rail. If this is the case, the processor asserts an override signal which is used by a logic circuit to force the power supply to remain on in the sleep state. A set of switches disconnect the main rails from other components which can be turned off in the sleep state. A select circuit selects one of the main rails to power the memory modules.

公开(公告)号：US11966270B2

公开(公告)日：2024-04-23

申请号：US17872332

申请日：2022-07-25

申请人： Seiko Group Corporation

发明人： Ryosuke Isogai ,  Yoshifumi Yoshida

IPC分类号： G06F1/32 ,  G06F1/3225 ,  G06F1/3287

CPC分类号： G06F1/3225 ,  G06F1/3287

摘要： There are provided a sensor data collection device, a sensor data collection system, and a method of collecting sensor data capable of reducing a drain of a battery due to standby power. The sensor data collection device includes a power supply, a power supply control circuit configured to control the power supply, a sensor configured to perform sensing to thereby obtain data, a memory configured to store the data obtained by the sensor, and a control circuit configured to control the power supply control circuit, the sensor, and the memory. The power supply control circuit supplies the sensor, the memory, and the control circuit with electrical power supplied by the power supply, and the control circuit makes the transition to any one of a plurality of operating states, and makes the power supply control circuit shut off the electrical power supplied by the power supply after a first operating state is completed and before the transition to a second operating state is made wherein the first operating state and the second operating state are included in the plurality of operating states.

公开(公告)号：US11880256B2

公开(公告)日：2024-01-23

申请号：US17829563

申请日：2022-06-01

申请人： Western Digital Technologies, Inc.

发明人： Ramanathan Muthiah

IPC分类号： G06F1/3225 ,  G06F3/06

CPC分类号： G06F1/3225 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679

摘要： A data storage device and method for energy feedback and report generation are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to maintain an association between logical addresses and application identifiers of applications on a host; determine power implications associated with a command to access a logical address of the memory; generate a report on the power implications, wherein the report identifies an application identifier associated with the logical address; and provide the report to the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

公开(公告)号：US11841756B2

公开(公告)日：2023-12-12

申请号：US17559289

申请日：2021-12-22

申请人： SK hynix Inc.

发明人： Lan Feng Wang ,  Won Kyoo Lee

IPC分类号： G06F1/3225 ,  G06F1/3234 ,  G06F13/16 ,  G06F13/42 ,  G06F13/38

CPC分类号： G06F1/3225 ,  G06F1/3275 ,  G06F13/1668 ,  G06F13/382 ,  G06F13/4221

摘要： A method for information configuration in power mode change for an interconnection protocol, a controller, and a storage device. The method can be used in a first device capable of linking to a second device according to the interconnection protocol. The method includes: while a hardware protocol engine of the first device for implementing a protocol layer of the interconnection protocol performs power mode change according to the protocol layer, generating a configuration indication signal to trigger a piece of firmware of the first device for performing information configuration for a physical layer of the interconnection protocol; in response to the configuration indication signal, performing the information configuration for the physical layer by the piece of firmware; and upon completion of the information configuration for the physical layer, informing, by the piece of firmware, the hardware protocol engine of the completion of the information configuration.

公开(公告)号：US20230350482A1

公开(公告)日：2023-11-02

申请号：US17272055

申请日：2020-12-17

申请人： Micron Technology, Inc.

发明人： Tao Xiong ,  Guang Chang Ye ,  Jizhe Xing ,  Jun Shen

IPC分类号： G06F1/3234 ,  G06F1/3225 ,  G11C5/14

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  G11C5/14 ,  G11C2207/2227

摘要： Various embodiments described herein provide for a method for reduced power consumption by a memory system. A memory system of some embodiments monitors power state change requests received by the memory system from a host system, and determines a pattern of power state change requests received from the host system. Based on the determined pattern, the memory system can decide to activate or deactivate a reduced power consumption mode on the memory system. A reduced power consumption mode can comprise a first set of operation parameters that cause a memory system to operate with lower power consumption than a second set of operation parameters associated with a current operation mode, where the current operation mode is associated with a current power state set or last requested by the host system.

公开(公告)号：US11782827B2

公开(公告)日：2023-10-10

申请号：US17554328

申请日：2021-12-17

申请人： KYOCERA Corporation

发明人： Toshikazu Hiramoto ,  Kazuyuki Takaki

IPC分类号： G06F12/02 ,  G06F1/3225

CPC分类号： G06F12/0246 ,  G06F1/3225

摘要： An electronic device includes a NAND flash memory device, a memory controller that issues a command for performing either erasing or writing of data to the NAND flash memory device, and a voltage monitor that monitors a power supply and detects a voltage drop. When the voltage drop is detected before an issue of the command, the memory controller ceases the issue of the command to the NAND flash memory device.