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    Multipage preparation commands for non-volatile memory systems
    4.
    发明授权
    Multipage preparation commands for non-volatile memory systems 有权
    用于非易失性存储器系统的多页准备命令

    公开(公告)号：US08806151B2

    公开(公告)日：2014-08-12

    申请号：US13676729

    申请日：2012-11-14

    Applicant: Apple Inc.

    Inventor： Vadim Khmelnitsky ,  Nir Jacob Wakrat ,  Tahoma Toelkes ,  Daniel Jeffrey Post ,  Anthony Fai

    IPC: G06F13/00 ,  G06F13/28 ,  G06F12/02

    CPC classification number: G06F12/0246

    Abstract: Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation.

    Abstract translation: 公开了用于非易失性存储器系统的多位准备命令。 多功能准备命令提供可用于准备非易失性存储器设备的数据，用于即将进行的多页程序操作。 主机控制器可以使用多页面程序操作之前的命令来优化多页面程序命令的使用。 非易失性存储器件可以使用这些命令来配置非易失性存储器以准备随后的操作，例如改变命令顺序或使用用于后续操作的最优化的命令集。

    Systems and methods for proactively refreshing nonvolatile memory
    5.
    发明授权
    Systems and methods for proactively refreshing nonvolatile memory 有权
    用于主动刷新非易失性存储器的系统和方法

    公开(公告)号：US09384089B2

    公开(公告)日：2016-07-05

    申请号：US14144957

    申请日：2013-12-31

    Applicant: Apple Inc.

    Inventor： Anthony Fai

    IPC: G06F11/07 ,  G06F11/10 ,  G11C11/406 ,  G11C16/34 ,  G11C29/08

    CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/106 ,  G11C11/406 ,  G11C11/40618 ,  G11C16/3418 ,  G11C29/08

    Abstract: System and methods for proactively refreshing portions of a nonvolatile memory including a memory system that proactively refreshes a portion of nonvolatile memory based on data associated with the portion. The data may include the time elapsed since the portion was last refreshed, the number of times the portion has been cycled, and the average operating temperature of the nonvolatile memory. A portion of nonvolatile memory, when meeting certain criteria determined from the data, may be proactively refreshed during a downtime when the nonvolatile memory is not otherwise being accessed.

    Abstract translation: 用于主动刷新非易失性存储器的部分的系统和方法，所述非易失性存储器包括基于与所述部分相关联的数据来主动刷新非易失性存储器的一部分的存储器系统。 数据可以包括自该部分最后刷新以来经过的时间，该部分已循环的次数以及该非易失性存储器的平均工作温度。 当非易失性存储器未被访问时，非易失性存储器的一部分当满足从数据确定的某些标准时可以在停机期间主动刷新。

    Systems and methods for improved communications in a nonvolatile memory system
    6.
    发明授权
    Systems and methods for improved communications in a nonvolatile memory system 有权
    用于改进非易失性存储器系统中的通信的系统和方法

    公开(公告)号：US09164680B2

    公开(公告)日：2015-10-20

    申请号：US14147700

    申请日：2014-01-06

    Applicant: Apple Inc.

    Inventor： Nicholas C. Seroff ,  Anthony Fai ,  Nir Jacob Wakrat

    IPC: G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16

    CPC classification number: G06F3/0611 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0635 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F13/1684 ,  G06F2212/7204 ,  Y02D10/154

    Abstract: Systems and methods are provided for improved communications in a nonvolatile memory (“NVM”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels.

    Abstract translation: 提供了用于在非易失性存储器（“NVM”）系统中改善通信的系统和方法。 系统可以在多个通信通道之间切换，以提供主机设备与系统中包含的NVM管芯之间的点对点通信。 主机设备可以在扩展到系统的一个或多个存储器控制器的多个通信通道之间切换，并且存储器控制器可以在延伸到NVM管芯的多个通信通道之间切换。 功率岛可以并入到系统中以电隔离与非活动通信信道相关联的系统组件。

    Method of selective power cycling of components in a memory device independently by turning off power to a memory array or memory controller
    7.
    发明授权
    Method of selective power cycling of components in a memory device independently by turning off power to a memory array or memory controller 有权
    通过关闭存储器阵列或存储器控制器的电源来独立地选择性地对存储器件中的组件进行功率循环的方法

    公开(公告)号：US08612791B2

    公开(公告)日：2013-12-17

    申请号：US13918240

    申请日：2013-06-14

    Applicant: Apple Inc.

    Inventor： Nir Jacob Wakrat ,  Anthony Fai ,  Matthew Byom

    IPC: G06F1/00

    CPC classification number: G06F1/3275 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14

    Abstract: In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.

    Abstract translation: 在非易失性存储器系统中，物理上分离的电源轨从主机系统提供给NVM设备，用于独立地对NVM设备中的控制器和存储器阵列进行电力循环。 NVM设备的控制器可以通过主机通道向主机系统发送电源循环请求信号，或更新NVM设备中的状态寄存器。 主机系统接收并解码电源周期请求信号，或读取状态寄存器，并执行电源循环请求，其中可以包括对NVM设备中的控制器或存储器阵列进行电源循环，或两者兼而有之。 功率循环请求可以基于非易失性存储器系统的功率状态，其可以由控制器或主机系统管理，或两者兼而有之。

    ARCHITECTURE FOR ADDRESS MAPPING OF MANAGED NON-VOLATILE MEMORY
    8.
    发明申请
    ARCHITECTURE FOR ADDRESS MAPPING OF MANAGED NON-VOLATILE MEMORY 有权
    管理非易失性存储器地址映射的架构

    公开(公告)号：US20130212318A1

    公开(公告)日：2013-08-15

    申请号：US13725671

    申请日：2012-12-21

    Applicant: Apple Inc.

    Inventor： Tahoma Toelkes ,  Nir Jacob Wakrat ,  Kenneth L. Herman ,  Barry Corlett ,  Vadim Khmelnitsky ,  Anthony Fai ,  Daniel Jeffrey Post ,  Hsiao Thio

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F12/0607 ,  G06F2212/1016 ,  G06F2212/7208

    Abstract: The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.

    Abstract translation: 所公开的架构使用地址映射将主机接口上的块地址映射到非易失性存储器（NVM）设备的内部块地址。 块地址映射到用于选择由块地址标识的可并行寻址单元（CAU）的内部芯片选择。 所公开的架构支持用于读取，写入，擦除和获取状态操作的通用NVM命令。 该架构还支持扩展命令集，以支持利用多个CAU架构的读写操作。

    Architecture for address mapping of managed non-volatile memory
    10.
    发明授权
    Architecture for address mapping of managed non-volatile memory 有权
    托管非易失性存储器的地址映射架构

    公开(公告)号：US08862851B2

    公开(公告)日：2014-10-14

    申请号：US13725671

    申请日：2012-12-21

    Applicant: Apple Inc.

    Inventor： Tahoma Toelkes ,  Nir Jacob Wakrat ,  Kenneth L Herman ,  Barry Corlett ,  Vadim Khmelnitsky ,  Anthony Fai ,  Daniel Jeffrey Post ,  Hsiao Thio

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/02 ,  G06F12/06

    CPC classification number: G06F12/0246 ,  G06F12/0607 ,  G06F2212/1016 ,  G06F2212/7208

    Abstract: The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.

    Abstract translation: 所公开的架构使用地址映射将主机接口上的块地址映射到非易失性存储器（NVM）设备的内部块地址。 块地址映射到用于选择由块地址标识的可并行寻址单元（CAU）的内部芯片选择。 所公开的架构支持用于读取，写入，擦除和获取状态操作的通用NVM命令。 该架构还支持扩展命令集，以支持利用多个CAU架构的读写操作。

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