公开(公告)号：US11755328B2

公开(公告)日：2023-09-12

申请号：US17527872

申请日：2021-11-16

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

CPC classification number: G06F9/3814 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/3877 ,  G06F9/4881 ,  G06F9/522

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US11210100B2

公开(公告)日：2021-12-28

申请号：US16242151

申请日：2019-01-08

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US12242855B2

公开(公告)日：2025-03-04

申请号：US18361212

申请日：2023-07-28

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US20240036870A1

公开(公告)日：2024-02-01

申请号：US18361212

申请日：2023-07-28

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

CPC classification number: G06F9/3814 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/3877 ,  G06F9/4881 ,  G06F9/522

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US11829763B2

公开(公告)日：2023-11-28

申请号：US16539684

申请日：2019-08-13

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Viney Gautam ,  Wei-Han Lien ,  Kulin N. Kothari ,  Mridul Agarwal

IPC: G06F9/345 ,  G06F9/38 ,  G06F9/30 ,  G06F9/50 ,  G06F12/0802

CPC classification number: G06F9/3455 ,  G06F9/30043 ,  G06F9/3861 ,  G06F9/5005 ,  G06F12/0802

Abstract: A system and method for efficiently reducing the latency of load operations. In various embodiments, logic of a processor accesses a prediction table after fetching instructions. For a prediction table hit, the logic executes a load instruction with a retrieved predicted address from the prediction table. For a prediction table miss, when the logic determines the address of the load instruction and hits in a learning table, the logic updates a level of confidence indication to indicate a higher level of confidence when a stored address matches the determined address. When the logic determines the level of confidence indication stored in a given table entry of the learning table meets a threshold, the logic allocates, in the prediction table, information stored in the given entry. Therefore, the predicted address is available during the next lookup of the prediction table.

公开(公告)号：US20220137975A1

公开(公告)日：2022-05-05

申请号：US17527872

申请日：2021-11-16

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US20210049015A1

公开(公告)日：2021-02-18

申请号：US16539684

申请日：2019-08-13

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Viney Gautam ,  Wei-Han Lien ,  Kulin N. Kothari ,  Mridul Agarwal

IPC: G06F9/345 ,  G06F9/38 ,  G06F9/30 ,  G06F9/50 ,  G06F12/0802

Abstract: A system and method for efficiently reducing the latency of load operations. In various embodiments, logic of a processor accesses a prediction table after fetching instructions. For a prediction table hit, the logic executes a load instruction with a retrieved predicted address from the prediction table. For a prediction table miss, when the logic determines the address of the load instruction and hits in a learning table, the logic updates a level of confidence indication to indicate a higher level of confidence when a stored address matches the determined address. When the logic determines the level of confidence indication stored in a given table entry of the learning table meets a threshold, the logic allocates, in the prediction table, information stored in the given entry. Therefore, the predicted address is available during the next lookup of the prediction table.

公开(公告)号：US20200218540A1

公开(公告)日：2020-07-09

申请号：US16242151

申请日：2019-01-08

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.