公开(公告)号：US20170269844A1

公开(公告)日：2017-09-21

申请号：US15190216

申请日：2016-06-23

Applicant: Apple Inc.

Inventor： Alexander Paley ,  Yuhua Liu

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/065 ,  G06F3/0619 ,  G06F3/0679 ,  G06F11/1446 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/202 ,  G06F2212/7201

Abstract: An apparatus includes an interface and a processor. The interface is configured to communicate with a non-volatile memory. The processor is configured to hold a translation table that maps between logical addresses and respective physical addresses in the non-volatile memory, to back-up to the non-volatile memory a baseline version of the translation table in one or more bulks, to additionally back-up to the non-volatile memory one or more incremental updates, which specify changes relative to the baseline version of the translation table caused by subsequent storage operations, to determine a maximal number of the incremental updates that, when recovered together with the baseline version from the non-volatile memory and replayed in the processor, meets a target recovery time of the translation table, and to set a number of the backed-up incremental updates to not exceed the maximal number.

公开(公告)号：US20200381060A1

公开(公告)日：2020-12-03

申请号：US16429021

申请日：2019-06-02

Applicant: Apple Inc.

Inventor： Muhammad N. Ashraf ,  Alexander Paley ,  Yuhua Liu ,  Vadim Khmelnitsky ,  Matthew J. Byom

IPC: G11C16/22 ,  G06F1/30 ,  G11C7/10 ,  G11C16/16

Abstract: Systems and methods for managing non-volatile memory devices are provided. Embodiments discussed herein provide rapid restart protection for journaling system. The rapid restart protection prevents the NVM from experiencing memory saturation when the NVM system is being forced to handle multiple successive restarts.

公开(公告)号：US11132145B2

公开(公告)日：2021-09-28

申请号：US16124154

申请日：2018-09-06

Applicant: Apple Inc.

Inventor： Yuhua Liu ,  Andrew W. Vogan ,  Matthew J. Byom ,  Alexander Paley

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06

Abstract: Disclosed herein are techniques for reducing write amplification when processing write commands directed to a non-volatile memory. According to some embodiments, the method can include the steps of (1) receiving a first plurality of write commands and a second plurality of write commands, where the first plurality of write commands and the second plurality of write commands are separated by a fence command (2) caching the first plurality of write commands, the second plurality of write commands, and the fence command, and (3) in accordance with the fence command, and in response to identifying that at least one condition is satisfied: (i) issuing the first plurality of write commands to the non-volatile memory, (ii) issuing the second plurality of write commands to the non-volatile memory, and (iii) updating log information to reflect that the first plurality of write commands precede the second plurality of write commands.

公开(公告)号：US11094381B2

公开(公告)日：2021-08-17

申请号：US16429021

申请日：2019-06-02

Applicant: Apple Inc.

Inventor： Muhammad N. Ashraf ,  Alexander Paley ,  Yuhua Liu ,  Vadim Khmelnitsky ,  Matthew J. Byom

IPC: G11C16/22 ,  G11C16/16 ,  G11C7/10 ,  G06F1/30

Abstract: Systems and methods for managing non-volatile memory devices are provided. Embodiments discussed herein provide rapid restart protection for journaling system. The rapid restart protection prevents the NVM from experiencing memory saturation when the NVM system is being forced to handle multiple successive restarts.

公开(公告)号：US10162561B2

公开(公告)日：2018-12-25

申请号：US15190216

申请日：2016-06-23

Applicant: Apple Inc.

Inventor： Alexander Paley ,  Yuhua Liu

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/02 ,  G06F11/14

Abstract: An apparatus includes an interface and a processor. The interface is configured to communicate with a non-volatile memory. The processor is configured to hold a translation table that maps between logical addresses and respective physical addresses in the non-volatile memory, to back-up to the non-volatile memory a baseline version of the translation table in one or more bulks, to additionally back-up to the non-volatile memory one or more incremental updates, which specify changes relative to the baseline version of the translation table caused by subsequent storage operations, to determine a maximal number of the incremental updates that, when recovered together with the baseline version from the non-volatile memory and replayed in the processor, meets a target recovery time of the translation table, and to set a number of the backed-up incremental updates to not exceed the maximal number.