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公开(公告)号:US12073897B2
公开(公告)日:2024-08-27
申请号:US18300091
申请日:2023-04-13
发明人: Marco Casarsa
CPC分类号: G11C29/023 , G06F12/023 , G06F2212/202
摘要: A random access memory (RAM) includes an array of arranged in rows and columns. The rows of the storage elements correspond to respective memory locations of the RAM. The storage elements of a row have a common gated-clock input and respective data inputs, and each row of the array of storage elements includes a plurality of D type latches. In operation, an address input of the RAM receives a memory address identifying a memory location in the RAM. Clock gating circuitry of the RAM, generates respective gated-clock signals for the rows of the array of storage elements based on the memory address received at the address input. Memory operation are performed using storage elements of the array based on the gated-clock signals.
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公开(公告)号:US12045254B2
公开(公告)日:2024-07-23
申请号:US18170225
申请日:2023-02-16
申请人: Ocient Inc.
IPC分类号: G06F16/00 , G06F12/02 , G06F13/16 , G06F13/28 , G06F13/42 , G06F15/173 , G06F16/22 , G06F16/23 , G06F16/25 , G06F16/27 , G06F16/28 , H04L67/1097 , H04L67/568 , G06F3/06
CPC分类号: G06F16/27 , G06F12/0238 , G06F13/1673 , G06F13/28 , G06F13/4282 , G06F15/17331 , G06F16/22 , G06F16/2358 , G06F16/2365 , G06F16/25 , G06F16/285 , H04L67/1097 , H04L67/568 , G06F3/0656 , G06F3/067 , G06F2212/202 , G06F2213/0026 , G06F2213/0032
摘要: A payload store within a database management system includes a first set of nodes that include a first node that includes a memory, a network interface, a storage device, and a processing unit. The processing unit receives, via the network interface, a first portion of data to be stored in a plurality of storage devices of the first set of nodes, and splits the first portion into a first set of data rows that includes a plurality of subsets of data rows and a last subset of data rows. The processing unit further randomly assigns the plurality of subsets of data rows and the last subset of data rows between the first set of nodes and stores a first number of data rows in the storage device. The processing unit further sends, via the network interface, a second number of data rows to the second node for storage therein.
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公开(公告)号:US12040889B2
公开(公告)日:2024-07-16
申请号:US18076104
申请日:2022-12-06
申请人: Intel Corporation
发明人: Matthew Adiletta , Aaron Gorius , Myles Wilde , Michael Crocker
IPC分类号: H04L41/14 , G02B6/38 , G02B6/42 , G02B6/44 , G06F1/18 , G06F1/20 , G06F3/06 , G06F8/65 , G06F9/30 , G06F9/4401 , G06F9/54 , G06F12/109 , G06F12/14 , G06F13/16 , G06F13/40 , G06F15/16 , G06F16/901 , G08C17/02 , G11C5/02 , G11C7/10 , G11C11/56 , G11C14/00 , H03M7/30 , H03M7/40 , H04B10/25 , H04L43/08 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L49/00 , H04L49/25 , H04L49/356 , H04L49/45 , H04L67/02 , H04L67/306 , H04L69/04 , H04L69/329 , H04Q11/00 , H05K7/14 , B25J15/00 , B65G1/04 , G05D23/19 , G05D23/20 , G06F9/38 , G06F9/50 , G06F11/14 , G06F11/34 , G06F12/0862 , G06F12/0893 , G06F12/10 , G06F13/42 , G06F15/80 , G06Q10/06 , G06Q10/0631 , G06Q10/087 , G06Q10/20 , G06Q50/04 , G07C5/00 , G11C5/06 , H04J14/00 , H04L9/06 , H04L9/14 , H04L9/32 , H04L12/28 , H04L41/02 , H04L41/046 , H04L41/0813 , H04L41/082 , H04L41/0896 , H04L41/12 , H04L41/147 , H04L41/5019 , H04L43/065 , H04L43/16 , H04L45/02 , H04L45/52 , H04L47/24 , H04L47/38 , H04L47/70 , H04L47/765 , H04L47/78 , H04L47/80 , H04L49/15 , H04L49/55 , H04L61/00 , H04L67/00 , H04L67/10 , H04L67/1004 , H04L67/1008 , H04L67/1012 , H04L67/1014 , H04L67/1029 , H04L67/1034 , H04L67/1097 , H04L67/12 , H04L67/51 , H04Q1/04 , H04W4/02 , H04W4/80 , H05K1/02 , H05K1/18 , H05K5/02 , H05K7/20 , H05K13/04
CPC分类号: H04L43/08 , G02B6/3882 , G02B6/3893 , G02B6/3897 , G02B6/4292 , G02B6/4452 , G06F1/183 , G06F1/20 , G06F3/0613 , G06F3/0625 , G06F3/064 , G06F3/0653 , G06F3/0655 , G06F3/0664 , G06F3/0665 , G06F3/0673 , G06F3/0679 , G06F3/0683 , G06F3/0688 , G06F3/0689 , G06F8/65 , G06F9/30036 , G06F9/4401 , G06F9/544 , G06F12/109 , G06F12/1408 , G06F13/1668 , G06F13/4022 , G06F13/4068 , G06F13/409 , G06F15/161 , G06F16/9014 , G08C17/02 , G11C5/02 , G11C7/1072 , G11C11/56 , G11C14/0009 , H03M7/3086 , H03M7/4056 , H03M7/4081 , H04B10/25891 , H04L41/145 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L49/00 , H04L49/25 , H04L49/357 , H04L49/45 , H04L67/02 , H04L67/306 , H04L69/04 , H04L69/329 , H04Q11/0003 , H05K7/1442 , B25J15/0014 , B65G1/0492 , G05D23/1921 , G05D23/2039 , G06F3/061 , G06F3/0611 , G06F3/0616 , G06F3/0619 , G06F3/0631 , G06F3/0638 , G06F3/0647 , G06F3/0658 , G06F3/0659 , G06F3/067 , G06F9/3887 , G06F9/5016 , G06F9/5044 , G06F9/505 , G06F9/5072 , G06F9/5077 , G06F11/141 , G06F11/3414 , G06F12/0862 , G06F12/0893 , G06F12/10 , G06F13/161 , G06F13/1694 , G06F13/42 , G06F13/4282 , G06F15/8061 , G06F2209/5019 , G06F2209/5022 , G06F2212/1008 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/152 , G06F2212/202 , G06F2212/401 , G06F2212/402 , G06F2212/7207 , G06Q10/06 , G06Q10/06314 , G06Q10/087 , G06Q10/20 , G06Q50/04 , G07C5/008 , G08C2200/00 , G11C5/06 , H03M7/30 , H03M7/3084 , H03M7/40 , H03M7/4031 , H03M7/6005 , H03M7/6023 , H04B10/25 , H04J14/00 , H04L9/0643 , H04L9/14 , H04L9/3247 , H04L9/3263 , H04L12/2809 , H04L41/024 , H04L41/046 , H04L41/0813 , H04L41/082 , H04L41/0896 , H04L41/12 , H04L41/147 , H04L41/5019 , H04L43/065 , H04L43/16 , H04L45/02 , H04L45/52 , H04L47/24 , H04L47/38 , H04L47/765 , H04L47/782 , H04L47/805 , H04L47/82 , H04L47/823 , H04L49/15 , H04L49/555 , H04L61/00 , H04L67/10 , H04L67/1004 , H04L67/1008 , H04L67/1012 , H04L67/1014 , H04L67/1029 , H04L67/1034 , H04L67/1097 , H04L67/12 , H04L67/34 , H04L67/51 , H04Q1/04 , H04Q11/00 , H04Q11/0005 , H04Q2011/0037 , H04Q2011/0041 , H04Q2011/0052 , H04Q11/0062 , H04Q11/0071 , H04Q2011/0073 , H04Q2011/0079 , H04Q2011/0086 , H04Q2213/13523 , H04Q2213/13527 , H04W4/023 , H04W4/80 , H05K1/0203 , H05K1/181 , H05K5/0204 , H05K7/1418 , H05K7/1421 , H05K7/1422 , H05K7/1447 , H05K7/1461 , H05K7/1485 , H05K7/1487 , H05K7/1489 , H05K7/1491 , H05K7/1492 , H05K7/1498 , H05K7/2039 , H05K7/20709 , H05K7/20727 , H05K7/20736 , H05K7/20745 , H05K7/20836 , H05K13/0486 , H05K2201/066 , H05K2201/10121 , H05K2201/10159 , H05K2201/10189 , Y02D10/00 , Y02P90/30 , Y04S10/50 , Y04S10/52 , Y10S901/01
摘要: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.
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公开(公告)号:US20240193084A1
公开(公告)日:2024-06-13
申请号:US18504545
申请日:2023-11-08
申请人: FLC Global, Ltd.
发明人: Sehat Sutardja
IPC分类号: G06F12/0811 , G06F3/06 , G06F9/4401 , G06F12/06 , G06F12/0804 , G06F12/0813 , G06F12/0862 , G06F12/0864 , G06F12/0868 , G06F12/0897 , G06F12/10 , G06F12/1027 , G11C11/406
CPC分类号: G06F12/0811 , G06F3/061 , G06F3/0613 , G06F3/0638 , G06F3/0655 , G06F3/0656 , G06F3/0679 , G06F3/0683 , G06F9/4406 , G06F12/0804 , G06F12/0813 , G06F12/0862 , G06F12/0864 , G06F12/0868 , G06F12/0897 , G06F12/10 , G06F12/1027 , G11C11/40607 , G06F12/0607 , G06F2212/1016 , G06F2212/1021 , G06F2212/152 , G06F2212/154 , G06F2212/161 , G06F2212/171 , G06F2212/20 , G06F2212/202 , G06F2212/214 , G06F2212/22 , G06F2212/222 , G06F2212/251 , G06F2212/305 , G06F2212/50 , G06F2212/60 , G06F2212/6022 , G06F2212/6032 , G06F2212/608 , G06F2212/62 , Y02D10/00
摘要: A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.
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公开(公告)号:US11971818B1
公开(公告)日:2024-04-30
申请号:US17863985
申请日:2022-07-13
发明人: Steven L. Gregor , Puneet Arora
CPC分类号: G06F12/08 , G11C29/44 , G06F2212/202 , G11C29/48
摘要: A memory view generator evaluates a Liberty file characterizing an NVM module to generate a memory view file for the NVM module. The memory view file includes a port alias identifying ports of the NVM module. The port alias for a set of ports of the NVM module characterizes a type of port in the set of ports. The memory view file includes a port action identifying ports of the NVM module that have a static value and a port access identifying ports of the NVM module that have a dynamic value. The memory view file has an address limit characterizing a number of words in the NVM module and an address partition characterizing address bits and data bits. The memory view file includes a read delay that defines a number of clock cycles needed to hold an address bus stable after a strobe port transitions to an inactive state.
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公开(公告)号:US11907200B2
公开(公告)日:2024-02-20
申请号:US17037445
申请日:2020-09-29
CPC分类号: G06F16/2365 , G06F11/1441 , G06F12/0804 , G06F11/1666 , G06F11/20 , G06F12/0238 , G06F2212/202
摘要: Apparatuses, systems, methods, and computer program products are disclosed for persistent memory management. Persistent memory management may include replicating a persistent data structure in volatile memory buffers of at least two non-volatile storage devices. Persistent memory management may include preserving a snapshot copy of data in association with completion of a barrier operation for the data. Persistent memory management may include determining which interface of a plurality of supported interfaces is to be used to flush data from a processor complex.
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公开(公告)号:US11836100B1
公开(公告)日:2023-12-05
申请号:US17807157
申请日:2022-06-16
申请人: Dell Products, L.P.
发明人: Austin P. Bolen , Komal Dhote , Manjunath A M
CPC分类号: G06F13/1684 , G06F12/0238 , G06F2212/202
摘要: According to one embodiment, an Information Handling System (IHS) includes at least one storage unit that conforms to an NVMe specification and first and second BMCs. The BMCs are in communication with the storage unit and each configured with computer-executable instructions to negotiate with the second BMC, whether first or second BMC is to be an active BMC such that the other of the first or second BMCs becomes a passive BMC. When the first BMC is the active BMC, allow shared commands to be issued to a storage unit conforming to a Non-Volatile Memory Express (NVMe) specification; otherwise, inhibit the shared commands from being issued to the storage unit.
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公开(公告)号:US20230195334A1
公开(公告)日:2023-06-22
申请号:US17559618
申请日:2021-12-22
CPC分类号: G06F3/0631 , G06F3/0604 , G06F3/067 , G06F12/0238 , G06F2212/202
摘要: Systems and methods are described herein for an efficient storage layout of recorded content associated with a particular user. Content segments, unique to the user and encoded/transcoded at different bit rates, may be stored/partitioned based on the likelihood of a particular bit rate version of content being requested by the user and a duration of playback for the content segment. Content that is more frequently requested may be concatenated in a single storage location on more high performance hardware. Further, content that is played back for a longer duration of playback may also be grouped together and stored on more high performance hardware. Content that is more likely to be played for only a short time may be stored within a plurality of storage containers.
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公开(公告)号:US10085358B2
公开(公告)日:2018-09-25
申请号:US15396646
申请日:2016-12-31
申请人: Intel Corporation
CPC分类号: H04Q11/0005 , B25J15/0014 , B65G1/0492 , G02B6/3882 , G02B6/3893 , G02B6/3897 , G02B6/4292 , G02B6/4452 , G05D23/1921 , G05D23/2039 , G06F1/183 , G06F3/061 , G06F3/0611 , G06F3/0613 , G06F3/0616 , G06F3/0619 , G06F3/0625 , G06F3/0631 , G06F3/0638 , G06F3/064 , G06F3/0647 , G06F3/0653 , G06F3/0655 , G06F3/0658 , G06F3/0659 , G06F3/0664 , G06F3/0665 , G06F3/067 , G06F3/0673 , G06F3/0679 , G06F3/0683 , G06F3/0688 , G06F3/0689 , G06F8/65 , G06F9/30036 , G06F9/3887 , G06F9/4401 , G06F9/5016 , G06F9/5044 , G06F9/505 , G06F9/5072 , G06F9/5077 , G06F9/544 , G06F11/141 , G06F11/3414 , G06F12/0862 , G06F12/0893 , G06F12/10 , G06F12/109 , G06F12/1408 , G06F13/161 , G06F13/1668 , G06F13/1694 , G06F13/4022 , G06F13/4068 , G06F13/409 , G06F13/42 , G06F13/4282 , G06F15/8061 , G06F16/9014 , G06F2209/5019 , G06F2209/5022 , G06F2212/1008 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/152 , G06F2212/202 , G06F2212/401 , G06F2212/402 , G06F2212/7207 , G06Q10/06 , G06Q10/06314 , G06Q10/087 , G06Q10/20 , G06Q50/04 , G07C5/008 , G08C17/02 , G08C2200/00 , G11C5/02 , G11C5/06 , G11C7/1072 , G11C11/56 , G11C14/0009 , H03M7/30 , H03M7/3084 , H03M7/3086 , H03M7/40 , H03M7/4031 , H03M7/4056 , H03M7/4081 , H03M7/6005 , H03M7/6023 , H04B10/25 , H04B10/2504 , H04L9/0643 , H04L9/14 , H04L9/3247 , H04L9/3263 , H04L12/2809 , H04L29/12009 , H04L41/024 , H04L41/046 , H04L41/0813 , H04L41/082 , H04L41/0896 , H04L41/12 , H04L41/145 , H04L41/147 , H04L41/5019 , H04L43/065 , H04L43/08 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L43/16 , H04L45/02 , H04L45/52 , H04L47/24 , H04L47/38 , H04L47/765 , H04L47/782 , H04L47/805 , H04L47/82 , H04L47/823 , H04L49/00 , H04L49/15 , H04L49/25 , H04L49/357 , H04L49/45 , H04L49/555 , H04L67/02 , H04L67/10 , H04L67/1004 , H04L67/1008 , H04L67/1012 , H04L67/1014 , H04L67/1029 , H04L67/1034 , H04L67/1097 , H04L67/12 , H04L67/16 , H04L67/306 , H04L67/34 , H04L69/04 , H04L69/329 , H04Q1/04 , H04Q11/00 , H04Q11/0003 , H04Q11/0062 , H04Q11/0071 , H04Q2011/0037 , H04Q2011/0041 , H04Q2011/0052 , H04Q2011/0073 , H04Q2011/0079 , H04Q2011/0086 , H04Q2213/13523 , H04Q2213/13527 , H04W4/023 , H04W4/80 , H05K1/0203 , H05K1/181 , H05K5/0204 , H05K7/1418 , H05K7/1421 , H05K7/1422 , H05K7/1442 , H05K7/1447 , H05K7/1461 , H05K7/1485 , H05K7/1487 , H05K7/1489 , H05K7/1491 , H05K7/1492 , H05K7/1498 , H05K7/2039 , H05K7/20709 , H05K7/20727 , H05K7/20736 , H05K7/20745 , H05K7/20836 , H05K13/0486 , H05K2201/066 , H05K2201/10121 , H05K2201/10159 , H05K2201/10189 , Y02D10/14 , Y02D10/151 , Y02P90/30 , Y04S10/54 , Y10S901/01
摘要: A sled for operation in a corresponding rack of a data center includes a chassis-less circuit board substrate having one or more physical resources coupled to a top side of the chassis-less circuit board and one or more memory devices coupled to a bottom side of the chassis-less circuit board. The sled does not include a housing or chassis and is opened to the local environment. In the illustrative embodiments, the sled may be embodied as a compute sled, an accelerator sled, or a storage sled.
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公开(公告)号:US10073774B2
公开(公告)日:2018-09-11
申请号:US15459866
申请日:2017-03-15
申请人: NetApp, Inc.
发明人: Mahmoud K. Jibbe , Keith Holt , Scott Terrill
CPC分类号: G06F12/0802 , G06F3/067 , G06F12/10 , G06F2212/1016 , G06F2212/202 , G06F2212/604 , G11B5/012 , G11B20/10527 , G11B2020/10657 , G11B2020/10675
摘要: A system and method for improving the management of data input and output (I/O) operations for Shingled Magnetic Recording (SMR) devices in a network storage system is disclosed. The storage system includes a storage controller that receives a series of write requests for data blocks to be written to non-sequential addresses within a pool of SMR devices. The storage controller writes the data blocks from the series of write requests to a corresponding sequence of data clusters allocated within a first data cache of the storage controller for a thinly provisioned volume of the pool of SMR devices. Upon determining that a current utilization of the first data cache's data storage capacity exceeds a threshold, the sequence of data clusters including the data blocks from the first data cache are transferred to sequential physical addresses within the SMR devices.
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