Random access memory and corresponding method for managing a random access memory

    公开(公告)号:US12073897B2

    公开(公告)日:2024-08-27

    申请号:US18300091

    申请日:2023-04-13

    发明人: Marco Casarsa

    IPC分类号: G11C29/02 G06F12/02

    摘要: A random access memory (RAM) includes an array of arranged in rows and columns. The rows of the storage elements correspond to respective memory locations of the RAM. The storage elements of a row have a common gated-clock input and respective data inputs, and each row of the array of storage elements includes a plurality of D type latches. In operation, an address input of the RAM receives a memory address identifying a memory location in the RAM. Clock gating circuitry of the RAM, generates respective gated-clock signals for the rows of the array of storage elements based on the memory address received at the address input. Memory operation are performed using storage elements of the array based on the gated-clock signals.

    Memory view for non-volatile memory module

    公开(公告)号:US11971818B1

    公开(公告)日:2024-04-30

    申请号:US17863985

    申请日:2022-07-13

    IPC分类号: G06F12/08 G11C29/44 G11C29/48

    摘要: A memory view generator evaluates a Liberty file characterizing an NVM module to generate a memory view file for the NVM module. The memory view file includes a port alias identifying ports of the NVM module. The port alias for a set of ports of the NVM module characterizes a type of port in the set of ports. The memory view file includes a port action identifying ports of the NVM module that have a static value and a port access identifying ports of the NVM module that have a dynamic value. The memory view file has an address limit characterizing a number of words in the NVM module and an address partition characterizing address bits and data bits. The memory view file includes a read delay that defines a number of clock cycles needed to hold an address bus stable after a strobe port transitions to an inactive state.

    Redundant baseboard management controller (BMC) system and method

    公开(公告)号:US11836100B1

    公开(公告)日:2023-12-05

    申请号:US17807157

    申请日:2022-06-16

    IPC分类号: G06F13/16 G06F12/02

    摘要: According to one embodiment, an Information Handling System (IHS) includes at least one storage unit that conforms to an NVMe specification and first and second BMCs. The BMCs are in communication with the storage unit and each configured with computer-executable instructions to negotiate with the second BMC, whether first or second BMC is to be an active BMC such that the other of the first or second BMCs becomes a passive BMC. When the first BMC is the active BMC, allow shared commands to be issued to a storage unit conforming to a Non-Volatile Memory Express (NVMe) specification; otherwise, inhibit the shared commands from being issued to the storage unit.

    METHOD AND SYSTEM FOR EFFICIENT LAYOUT OF STORED VIDEO SEGMENTS

    公开(公告)号:US20230195334A1

    公开(公告)日:2023-06-22

    申请号:US17559618

    申请日:2021-12-22

    IPC分类号: G06F3/06 G06F12/02

    摘要: Systems and methods are described herein for an efficient storage layout of recorded content associated with a particular user. Content segments, unique to the user and encoded/transcoded at different bit rates, may be stored/partitioned based on the likelihood of a particular bit rate version of content being requested by the user and a duration of playback for the content segment. Content that is more frequently requested may be concatenated in a single storage location on more high performance hardware. Further, content that is played back for a longer duration of playback may also be grouped together and stored on more high performance hardware. Content that is more likely to be played for only a short time may be stored within a plurality of storage containers.