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公开(公告)号：US10977119B2
公开(公告)日：2021-04-13
申请号：US16382046
申请日：2019-04-11
Applicant: Apple Inc.
Inventor： Eran Roll , Stas Mouler , Matthew J. Byom , Andrew W. Vogan , Muhammad N. Ashraf , Elad Harush , Roman Guy
Abstract: Disclosed are techniques for managing parity information for data stored on a storage device. A method can be implemented at a computing device communicably coupled to the storage device, and include (1) receiving a request to write data into a data band of the storage device, (2) writing the data into stripes of the data band, comprising, for each stripe of the data band: (i) calculating first parity information for the data written into the stripe, (ii) writing the first parity information into a volatile memory, and (iii) in response to determining that a threshold number of stripes have been written: converting the first parity information into smaller second parity information, and (3) in response to determining that the data band is read-verified: (i) converting the second parity information into smaller third parity information, and (ii) storing the smaller third parity information into a parity band of the storage device.
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Patent Agency Ranking
公开(公告)号：US20170277245A1
公开(公告)日：2017-09-28
申请号：US15219984
申请日：2016-07-26
Applicant: Apple Inc.
Inventor： Alexander Paley , Andrew W. Vogan , Eran Sandel , Lior Mouler , Liran Erez , Matthew J. Byom , Muhammad N. Ashraf , Roman Guy
CPC classification number: G06F1/3275 , G06F1/263 , G06F1/30 , G06F1/3287 , G06F11/00
Abstract: Systems and methods for handling sudden power failures in non-volatile memory devices such as solid state drives are provided by having the non-volatile memory device boot up in a low power write mode, which limits substantially all programming operations to a single level cell (SLC) mode, as opposed to a normal mode in which the programming operations can be performed in a multi-level cell (MLC) mode. Thus, if the system experiences a sudden power failure when it is being powered solely by AC derived power and the battery is below a level sufficient for powering the device while it is programming in the SLC mode, data integrity will be preserved because the programming operation was being performed in SLC mode. The non-volatile memory device may be permitted to exit out the low power write mode into the normal mode when the charge level of the battery is sufficient for powering the system.
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公开(公告)号：US11972143B2
公开(公告)日：2024-04-30
申请号：US17222978
申请日：2021-04-05
Applicant: Apple Inc.
Inventor： Matthew J. Byom , Tudor Antoniu , Alexander Paley , Andrew W. Vogan , Muhammad N. Ashraf
IPC: G06F3/06 , G06F12/0875
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0644 , G06F3/0679 , G06F12/0875 , G06F2212/1016
Abstract: Disclosed herein are techniques for balancing write commands directed to a non-volatile memory. According to some embodiments, a method may include caching a plurality of write commands into a write cache, and, in response to determining that an available capacity of the write cache satisfies a first threshold value: performing at least one write operation by directing data associated with the write commands in the write cache to the first partition of the non-volatile memory in response to determining that an available capacity of a first partition of the non-volatile memory satisfies a second threshold value; and performing at least one write operation by directing data associated with the write commands in the write cache to a second partition of the non-volatile memory in response to determining that the available capacity of the first partition of the non-volatile memory does not satisfy the second threshold value.
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公开(公告)号：US20200381060A1
公开(公告)日：2020-12-03
申请号：US16429021
申请日：2019-06-02
Applicant: Apple Inc.
Inventor： Muhammad N. Ashraf , Alexander Paley , Yuhua Liu , Vadim Khmelnitsky , Matthew J. Byom
Abstract: Systems and methods for managing non-volatile memory devices are provided. Embodiments discussed herein provide rapid restart protection for journaling system. The rapid restart protection prevents the NVM from experiencing memory saturation when the NVM system is being forced to handle multiple successive restarts.
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公开(公告)号：US11094381B2
公开(公告)日：2021-08-17
申请号：US16429021
申请日：2019-06-02
Applicant: Apple Inc.
Inventor： Muhammad N. Ashraf , Alexander Paley , Yuhua Liu , Vadim Khmelnitsky , Matthew J. Byom
Abstract: Systems and methods for managing non-volatile memory devices are provided. Embodiments discussed herein provide rapid restart protection for journaling system. The rapid restart protection prevents the NVM from experiencing memory saturation when the NVM system is being forced to handle multiple successive restarts.
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公开(公告)号：US09990023B2
公开(公告)日：2018-06-05
申请号：US15219984
申请日：2016-07-26
Applicant: Apple Inc.
Inventor： Alexander Paley , Andrew W. Vogan , Eran Sandel , Lior Mouler , Liran Erez , Matthew J. Byom , Muhammad N. Ashraf , Roman Guy
CPC classification number: G06F1/3275 , G06F1/263 , G06F1/30 , G06F1/3287 , G06F11/00
Abstract: Systems and methods for handling sudden power failures in non-volatile memory devices such as solid state drives are provided by having the non-volatile memory device boot up in a low power write mode, which limits substantially all programming operations to a single level cell (SLC) mode, as opposed to a normal mode in which the programming operations can be performed in a multi-level cell (MLC) mode. Thus, if the system experiences a sudden power failure when it is being powered solely by AC derived power and the battery is below a level sufficient for powering the device while it is programming in the SLC mode, data integrity will be preserved because the programming operation was being performed in SLC mode. The non-volatile memory device may be permitted to exit out the low power write mode into the normal mode when the charge level of the battery is sufficient for powering the system.
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