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公开(公告)号:US20200264792A1
公开(公告)日:2020-08-20
申请号:US16277230
申请日:2019-02-15
Applicant: Apple Inc.
Inventor: Alexander Paley , Andrew W. Vogan
IPC: G06F3/06
Abstract: Systems and methods for balancing multiple partitions of non-volatile memory devices are provided. Embodiments discussed herein execute a balance proportion scheme in connection with a NVM that is partitioned to have multiple partition types. Each partition type has an associated endurance that defines an average number of program/erase (P/E) cycles it can endure before it reaches failure. For example, a first partition type may have a substantially greater endurance than a second partition type. The balance proportion scheme ensures that, even though each partition type has a different associated endurance, all partition types are used proportionally with respect to each other to balance their respective P/E cycles. This way, both partition types will reach the upper limits of their respective endurance levels out at approximately the same time.
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2.
公开(公告)号:US20170269844A1
公开(公告)日:2017-09-21
申请号:US15190216
申请日:2016-06-23
Applicant: Apple Inc.
Inventor: Alexander Paley , Yuhua Liu
CPC classification number: G06F3/065 , G06F3/0619 , G06F3/0679 , G06F11/1446 , G06F12/0246 , G06F12/1009 , G06F2212/1016 , G06F2212/1032 , G06F2212/202 , G06F2212/7201
Abstract: An apparatus includes an interface and a processor. The interface is configured to communicate with a non-volatile memory. The processor is configured to hold a translation table that maps between logical addresses and respective physical addresses in the non-volatile memory, to back-up to the non-volatile memory a baseline version of the translation table in one or more bulks, to additionally back-up to the non-volatile memory one or more incremental updates, which specify changes relative to the baseline version of the translation table caused by subsequent storage operations, to determine a maximal number of the incremental updates that, when recovered together with the baseline version from the non-volatile memory and replayed in the processor, meets a target recovery time of the translation table, and to set a number of the backed-up incremental updates to not exceed the maximal number.
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公开(公告)号:US11579789B2
公开(公告)日:2023-02-14
申请号:US15721081
申请日:2017-09-29
Applicant: Apple Inc.
Inventor: Alexander Paley , Andrew W. Vogan
Abstract: Disclosed herein are techniques for managing context information for data stored within a non-volatile memory of a computing device. According to some embodiments, the method can include (1) loading, into a volatile memory of the computing device, the context information from the non-volatile memory, where the context information is separated into a plurality of silos, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: (i) identifying a next silo of the plurality of silos to be written into the non-volatile memory, (ii) updating the next silo to reflect the transactions that apply to the next silo, and (iii) writing the next silo into the non-volatile memory. In turn, when an inadvertent shutdown of the computing device occurs, the silos of which the context information is comprised can be sequentially accessed and restored in an efficient manner.
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公开(公告)号:US11256436B2
公开(公告)日:2022-02-22
申请号:US16277230
申请日:2019-02-15
Applicant: Apple Inc.
Inventor: Alexander Paley , Andrew W. Vogan
IPC: G06F3/06
Abstract: Systems and methods for balancing multiple partitions of non-volatile memory devices are provided. Embodiments discussed herein execute a balance proportion scheme in connection with a NVM that is partitioned to have multiple partition types. Each partition type has an associated endurance that defines an average number of program/erase (P/E) cycles it can endure before it reaches failure. For example, a first partition type may have a substantially greater endurance than a second partition type. The balance proportion scheme ensures that, even though each partition type has a different associated endurance, all partition types are used proportionally with respect to each other to balance their respective P/E cycles. This way, both partition types will reach the upper limits of their respective endurance levels out at approximately the same time.
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公开(公告)号:US12236119B2
公开(公告)日:2025-02-25
申请号:US17648540
申请日:2022-01-20
Applicant: Apple Inc.
Inventor: Alexander Paley , Andrew W. Vogan
IPC: G06F3/06
Abstract: Systems and methods for balancing multiple partitions of non-volatile memory devices are provided. Embodiments discussed herein execute a balance proportion scheme in connection with a NVM that is partitioned to have multiple partition types. Each partition type has an associated endurance that defines an average number of program/erase (P/E) cycles it can endure before it reaches failure. For example, a first partition type may have a substantially greater endurance than a second partition type. The balance proportion scheme ensures that, even though each partition type has a different associated endurance, all partition types are used proportionally with respect to each other to balance their respective P/E cycles. This way, both partition types will reach the upper limits of their respective endurance levels out at approximately the same time.
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6.
公开(公告)号:US11544159B2
公开(公告)日:2023-01-03
申请号:US17033420
申请日:2020-09-25
Applicant: Apple Inc.
Inventor: Alexander Paley , Andrew W. Vogan , Tudor Antoniu
Abstract: Disclosed are techniques for managing context information for data stored within a computing device. According to some embodiments, the method can include the steps of (1) loading, into a volatile memory of the computing device, the context information from a non-volatile memory of the computing device, where the context information is separated into a plurality of portions, and each portion of the plurality of portions is separated into a plurality of sub-portions, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: identifying a next sub-portion to be processed, where the next sub-portion is included in the plurality of sub-portions of a current portion being processed, identifying a portion of the context information that corresponds to the next sub-portion, converting the portion from a first format to a second format, and writing the portion into the non-volatile memory.
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公开(公告)号:US10379949B2
公开(公告)日:2019-08-13
申请号:US15721267
申请日:2017-09-29
Applicant: Apple Inc.
Inventor: Evgeny Televitckiy , Alexander Paley , Andrew W. Vogan
Abstract: Disclosed herein are techniques for managing parity information for data stored on a storage device. According to some embodiments, the method includes the steps of (1) receiving a request to store data into the storage device, (2) writing respective portions of the data into a plurality of data pages included in a first stripe of the storage device, where each data page is stored on a respective different die of the storage device, (3) calculating primary parity information for the first stripe, (4) writing the primary parity information into a primary parity page included in a second stripe of the storage device, (5) calculating secondary parity information for the second stripe, and (6) writing the secondary parity information into a secondary parity page included in a third stripe of the storage device. Additionally, a copy of the secondary parity information can be established to further-enhance redundancy.
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公开(公告)号:US20170277245A1
公开(公告)日:2017-09-28
申请号:US15219984
申请日:2016-07-26
Applicant: Apple Inc.
Inventor: Alexander Paley , Andrew W. Vogan , Eran Sandel , Lior Mouler , Liran Erez , Matthew J. Byom , Muhammad N. Ashraf , Roman Guy
CPC classification number: G06F1/3275 , G06F1/263 , G06F1/30 , G06F1/3287 , G06F11/00
Abstract: Systems and methods for handling sudden power failures in non-volatile memory devices such as solid state drives are provided by having the non-volatile memory device boot up in a low power write mode, which limits substantially all programming operations to a single level cell (SLC) mode, as opposed to a normal mode in which the programming operations can be performed in a multi-level cell (MLC) mode. Thus, if the system experiences a sudden power failure when it is being powered solely by AC derived power and the battery is below a level sufficient for powering the device while it is programming in the SLC mode, data integrity will be preserved because the programming operation was being performed in SLC mode. The non-volatile memory device may be permitted to exit out the low power write mode into the normal mode when the charge level of the battery is sufficient for powering the system.
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公开(公告)号:US11972143B2
公开(公告)日:2024-04-30
申请号:US17222978
申请日:2021-04-05
Applicant: Apple Inc.
Inventor: Matthew J. Byom , Tudor Antoniu , Alexander Paley , Andrew W. Vogan , Muhammad N. Ashraf
IPC: G06F3/06 , G06F12/0875
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0644 , G06F3/0679 , G06F12/0875 , G06F2212/1016
Abstract: Disclosed herein are techniques for balancing write commands directed to a non-volatile memory. According to some embodiments, a method may include caching a plurality of write commands into a write cache, and, in response to determining that an available capacity of the write cache satisfies a first threshold value: performing at least one write operation by directing data associated with the write commands in the write cache to the first partition of the non-volatile memory in response to determining that an available capacity of a first partition of the non-volatile memory satisfies a second threshold value; and performing at least one write operation by directing data associated with the write commands in the write cache to a second partition of the non-volatile memory in response to determining that the available capacity of the first partition of the non-volatile memory does not satisfy the second threshold value.
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公开(公告)号:US20200381060A1
公开(公告)日:2020-12-03
申请号:US16429021
申请日:2019-06-02
Applicant: Apple Inc.
Inventor: Muhammad N. Ashraf , Alexander Paley , Yuhua Liu , Vadim Khmelnitsky , Matthew J. Byom
Abstract: Systems and methods for managing non-volatile memory devices are provided. Embodiments discussed herein provide rapid restart protection for journaling system. The rapid restart protection prevents the NVM from experiencing memory saturation when the NVM system is being forced to handle multiple successive restarts.
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