公开(公告)号：US11455454B2

公开(公告)日：2022-09-27

申请号：US17103251

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Chien-Ju Chao ,  Pranavi Chandupatla ,  Saurabh Pijuskumar Sinha ,  Sheng-En Hung ,  Xiaoqing Xu

IPC: G06F30/00 ,  G06F30/394 ,  G06F30/392 ,  H01L25/065 ,  G06F30/3947

Abstract: According to one implementation of the present disclosure, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing respective inter-tier connections coupling for first and second networks concurrently on the generated 3D circuit design. The first networks may include power or ground networks, while the second networks may include signal networks. In another implementation, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing inter-tier connections on the generated 3D circuit design during one of a placement stage, a partitioning stage, a clock tree synthesis (CTS) stage, or a routing stage of a physical circuit design procedure.

公开(公告)号：US11228316B2

公开(公告)日：2022-01-18

申请号：US16522461

申请日：2019-07-25

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Saurabh Pijuskumar Sinha ,  Sheng-En Hung ,  Chien-Ju Chao

IPC: G05F1/04 ,  H03K3/00 ,  H03L7/08 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12

Abstract: Disclosed are methods, systems and devices for distribution of a timing signal among operational nodes of a circuit device comprising one or more circuit dies. In one implementation, a timing signal distribution network may transmit a timing signal to one or more operational circuit nodes formed on a circuit die and a clock circuit may generate a first clock signal for transmission as the timing signal to the one or more operational circuit nodes. A switch circuit may apply a second clock signal for transmission as the timing signal in lieu of the first clock signal if the circuit die is integrated at least one of the one or more other circuit dies. In another implementation, timing signals received at timing signal terminals of at least two of two or more of operational circuit nodes may be synchronized independently of the timing signal distribution network.

公开(公告)号：US20210028788A1

公开(公告)日：2021-01-28

申请号：US16522461

申请日：2019-07-25

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Saurabh Pijuskumar Sinha ,  Sheng-En Hung ,  Chien-Ju Chao

IPC: H03L7/08 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12

Abstract: Disclosed are methods, systems and devices for distribution of a timing signal among operational nodes of a circuit device comprising one or more circuit dies. In one implementation, a timing signal distribution network may transmit a timing signal to one or more operational circuit nodes formed on a circuit die and a clock circuit may generate a first clock signal for transmission as the timing signal to the one or more operational circuit nodes. A switch circuit may apply a second clock signal for transmission as the timing signal in lieu of the first clock signal if the circuit die is integrated at least one of the one or more other circuit dies. In another implementation, timing signals received at timing signal terminals of at least two of two or more of operational circuit nodes may be synchronized independently of the timing signal distribution network.

公开(公告)号：US20220164513A1

公开(公告)日：2022-05-26

申请号：US17103251

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Chien-Ju Chao ,  Pranavi Chandupatla ,  Saurabh Pijuskumar Sinha ,  Sheng-En Hung ,  Xiaoqing Xu

IPC: G06F30/392 ,  H01L25/065 ,  G06F30/3947

Abstract: According to one implementation of the present disclosure, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing respective inter-tier connections coupling for first and second networks concurrently on the generated 3D circuit design. The first networks may include power or ground networks, while the second networks may include signal networks. In another implementation, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing inter-tier connections on the generated 3D circuit design during one of a placement stage, a partitioning stage, a clock tree synthesis (CTS) stage, or a routing stage of a physical circuit design procedure.