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25 条记录 (耗时 0.012 秒)

    Clock pulse generation circuit
    1.
    发明授权
    Clock pulse generation circuit 有权

    公开(公告)号：US11038492B2

    公开(公告)日：2021-06-15

    申请号：US16544591

    申请日：2019-08-19

    申请人： Apple Inc.

    发明人： Steven F. Schicht ,  William R. Weier

    IPC分类号： G05F1/04 ,  H03K3/00 ,  H03K3/027 ,  H03K19/17736 ,  H03K19/00 ,  H03K3/017

    摘要： In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.

    Interface circuit and a clock output method therefor
    5.
    发明授权
    Interface circuit and a clock output method therefor 有权
    接口电路及其时钟输出方法

    公开(公告)号：US07724060B2

    公开(公告)日：2010-05-25

    申请号：US11736913

    申请日：2007-04-18

    申请人： Tetsuya Tokunaga ,  Hiroyuki Arai ,  Shuji Motegi ,  Takeshi Hibino ,  Takeshi Kimura

    发明人： Tetsuya Tokunaga ,  Hiroyuki Arai ,  Shuji Motegi ,  Takeshi Hibino ,  Takeshi Kimura

    IPC分类号： G05F1/04 ,  H03K3/00

    CPC分类号： G06F1/04

    摘要： An interface circuit outputting a clock signal and data to a data register configured to serially read in the data synchronously with the clock signal, in response to a change of a control signal for outputting the clock signal and the data from one logic level to the other logic level, the interface circuit comprising a clock output circuit configured to: detect a logic level of the clock signal when the control signal changes from the one logic level to the other logic level; output the clock signal on an as-is basis to the data register, when detecting one logic level of the clock signal; and output the clock signal after having changed from the other logic level to the one logic level, to the data register, when detecting the other logic level of the clock signal.

    摘要翻译： 一个接口电路，响应于用于输出时钟信号的控制信号和从一个逻辑电平到另一个逻辑电平的数据的变化，输出时钟信号和数据到数据寄存器，配置为与时钟信号同步地串行读取数据 逻辑电平，所述接口电路包括时钟输出电路，所述时钟输出电路被配置为：当所述控制信号从所述一个逻辑电平改变到另一逻辑电平时，检测所述时钟信号的逻辑电平; 当检测到时钟信号的一个逻辑电平时，将时钟信号原样输出到数据寄存器; 并且当检测到时钟信号的另一个逻辑电平时，在从另一个逻辑电平变为一个逻辑电平之后输出时钟信号到数据寄存器。

    Electronic device
    6.
    发明申请
    Electronic device 失效
    电子设备

    公开(公告)号：US20080054862A1

    公开(公告)日：2008-03-06

    申请号：US11893214

    申请日：2007-08-15

    申请人： Yasushi Hara ,  Akira Shiba ,  Yukihisa Taike

    发明人： Yasushi Hara ,  Akira Shiba ,  Yukihisa Taike

    IPC分类号： G05F1/04

    CPC分类号： H02M3/157

    摘要： An electronic device includes: a DC power source which supplies a first DC supply voltage; a DC voltage converter which is enabled or disabled in response to a first control signal, and which converts the first DC supply voltage into a second DC supply voltage different from the first DC supply voltage, when the DC voltage converter is enabled; a switch which selects and supplies either the first DC supply voltage or the second DC supply voltage as an output in response to a second control signal; a DC voltage regulator which is enabled or disabled in response to a third control signal, and which converts the DC supply voltage selected by the switch into a third supply voltage lower than the selected DC supply voltage when said DC voltage regulator is enabled; a control unit which provides the second control signal to the switch; and a loading which utilizes the third DC supply voltage. While the loading is operating intermittently, the control unit provides to the DC voltage converter the first control signal for disabling the DC voltage converter, provides to the switch the second control signal for selecting the first DC supply voltage, and provides to the DC voltage regulator the third control signal for enabling the DC voltage regulator.

    摘要翻译： 电子设备包括：提供第一直流电源电压的直流电源; DC电压转换器，其在响应于第一控制信号而被使能或禁用，并且当所述DC电压转换器被使能时，将所述第一DC电源电压转换成与所述第一DC电源电压不同的第二DC电源电压; 开关，其响应于第二控制信号选择并提供所述第一DC电源电压或所述第二DC电源电压作为输出; DC电压调节器，其响应于第三控制信号而被使能或禁用，并且当所述DC稳压器被使能时，将由开关选择的DC电源电压转换成低于所选择的DC电源电压的第三电源电压; 控制单元，向所述开关提供所述第二控制信号; 以及利用第三DC电源电压的负载。 当负载间歇运行时，控制单元向DC电压转换器提供用于禁用DC电压转换器的第一控制信号，向开关提供用于选择第一DC电源电压的第二控制信号，并提供给DC电压调节器 用于启用直流电压调节器的第三控制信号。

    Current limiting devices for alternating current systems
    7.
    发明授权
    Current limiting devices for alternating current systems 失效
    用于替代电流系统的电流限制器件

    公开(公告)号：US4045823A

    公开(公告)日：1977-08-30

    申请号：US648980

    申请日：1976-01-14

    申请人： Kenneth Charles Parton

    发明人： Kenneth Charles Parton

    IPC分类号： G05F3/06 ,  H02H9/02 ,  G05F1/04

    CPC分类号： H02H9/02 ,  G05F3/06 ,  H01F2029/143 ,  Y10S336/01 ,  Y10S505/85

    摘要： A current-limiting device for A.C. systems comprises saturable reactors with superconducting bias windings which maintain the reactors in saturation for normal A.C. loads. Excess current drives one of the reactors out of saturation on alternate half-cycles and thus creates a large flux change with accompanying back EMF to limit the current. The device is applicable to the connection of electric power distribution systems to limit fault currents and to allow power transfer without loss of stability.

    Sequenced pulse-width adjustment in a resonant clocking circuit
    8.
    发明授权
    Sequenced pulse-width adjustment in a resonant clocking circuit 有权

    公开(公告)号：US10141915B2

    公开(公告)日：2018-11-27

    申请号：US15479420

    申请日：2017-04-05

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Thomas J. Bucelot ,  Phillip J. Restle ,  David Wen-Hao Shan

    IPC分类号： G05F1/04 ,  H03K3/00 ,  H03K3/012 ,  H03K7/08 ,  G06F1/10 ,  H03K9/08 ,  H03K5/06 ,  G06F1/08

    摘要： A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.

    Clock processing logic and method for determining clock signal characteristics in reference voltage and temperature varying environments
    9.
    发明授权
    Clock processing logic and method for determining clock signal characteristics in reference voltage and temperature varying environments 有权
    用于确定参考电压和温度变化环境中的时钟信号特性的时钟处理逻辑和方法

    公开(公告)号：US07061294B1

    公开(公告)日：2006-06-13

    申请号：US11042395

    申请日：2005-01-25

    申请人： Cesar A. Talledo ,  Daniel R. Steinberg

    发明人： Cesar A. Talledo ,  Daniel R. Steinberg

    IPC分类号： G05F1/04 ,  H03K3/00

    CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C29/023 ,  G11C29/028

    摘要： Clock processing logic and method for determining clock signal characteristics in reference voltage and temperature varying environments are described. A sample vector is characterized by bit locations corresponding to sequentially increasing delay values so that values stored in such bit locations indicate clock signal edges where value transitions occur. In one embodiment, edge detection logic and sensitivity adjustment logic are used in determining the clock period from such a sample vector. In another embodiment, an edge filter, sample accumulation logic, and clock period and jitter processing logic are used in determining an average clock period and clock jitter from a predefined number of such sample vectors.

    摘要翻译： 描述用于确定参考电压和温度变化环境中的时钟信号特性的时钟处理逻辑和方法。 样本向量的特征在于对应于顺序增加的延迟值的比特位置，使得存储在这样的比特位置中的值指示出现值转换的时钟信号边缘。 在一个实施例中，边缘检测逻辑和灵敏度调整逻辑用于从这样的样本向量确定时钟周期。 在另一个实施例中，边缘滤波器，采样累积逻辑以及时钟周期和抖动处理逻辑被用于从预定数量的这种采样矢量确定平均时钟周期和时钟抖动。