公开(公告)号：US20220188038A1

公开(公告)日：2022-06-16

申请号：US17643732

申请日：2021-12-10

Applicant: Arm Limited

Inventor： Graeme Leslie INGRAM ,  Michael Jean SOLE ,  Erik PERSSON

IPC: G06F3/06 ,  G06F12/10

Abstract: A method for triggering prefetching of memory address translations for memory access requests to be issued by a memory access component of a processor in a data processing system to a memory management function in the data processing system is provided. The method includes obtaining command data from one or more memory access commands in a sequence of memory access commands for the memory access component, predicting one or more memory addresses, for which one or more memory address translations are likely to be required by the memory management function to process one or more memory access requests, from the obtained command data, in response to the predicting, performing one or more trigger operations to trigger a prefetch of the one or more memory address translations, using the predicted one or more memory addresses, in advance of the one or more memory access requests.

公开(公告)号：US20230161705A1

公开(公告)日：2023-05-25

申请号：US17532555

申请日：2021-11-22

Applicant: Arm Limited

Inventor： Graeme Leslie INGRAM ,  Michael Andrew CAMPBELL

IPC: G06F12/0871 ,  G06F12/0877 ,  G06F12/0808 ,  G06F12/02

CPC classification number: G06F12/0871 ,  G06F12/0877 ,  G06F12/0808 ,  G06F12/0246

Abstract: The present technique provides an apparatus and method for caching data. The apparatus has a cache storage to cache data associated with memory addresses, a first interface to receive access requests, where each access request is a request to access data at a memory address indicated by that access request, and a second interface to couple to a memory controller used to control access to memory. Further, cache control circuitry is used to control allocation of data into the cache storage in accordance with a power consumption based allocation policy that seeks to select which data is cached in the cache storage with the aim of conserving power associated with accesses to the memory via the second interface. A given access request considered by the cache control circuitry is provided with associated cache hint information providing one or more usage indications for given data at the memory address indicated by that given access request, and the cache control circuitry is arranged to reference the associated cache hint information when applying the power consumption based allocation policy to determine whether to cache the given data in the cache storage.

公开(公告)号：US20220365853A1

公开(公告)日：2022-11-17

申请号：US17807054

申请日：2022-06-15

Applicant: Arm Limited

Inventor： Andrew Brian Thomas HOPKINS ,  Graeme Leslie INGRAM ,  Elliot Maurice Simon ROSEMARINE ,  Antonio PRIORE

IPC: G06F11/14 ,  G06N3/04 ,  G06N3/08 ,  G06N3/063 ,  G06F9/48

Abstract: A method of performing fault detection during computations relating to a neural network comprising a first neural network layer and a second neural network layer in a data processing system, the method comprising: scheduling computations onto data processing resources for the execution of the first neural network layer and the second neural network layer, wherein the scheduling includes: for a given one of the first neural network layer and the second neural network layer, scheduling a respective given one of a first computation and a second computation as a non-duplicated computation, in which the given computation is at least initially scheduled to be performed only once during the execution of the given neural network layer; and for the other of the first and second neural network layers, scheduling the respective other of the first and second computations as a duplicated computation.