公开(公告)号：US20240248753A1

公开(公告)日：2024-07-25

申请号：US18099588

申请日：2023-01-20

Applicant: Arm Limited

Inventor： Elliot Maurice Simon ROSEMARINE ,  Alexander Eugene CHALFIN ,  Rune HOLM

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: A processor to: receive a task to be executed, the task comprising a task-based parameter associated with the task, for use in determining a position, within an array of data descriptors, of a particular data descriptor of a particular portion of data to be processed in executing the task. Each of the data descriptors in the array of data descriptors has a predetermined size and is indicative of a location in a storage system of a respective portion of data. The processor derives, based on the task, array location data indicative of a location in the storage system of a predetermined data descriptor, and obtains the particular data descriptor, based on the array location data and the task-based parameter. The processor obtains the particular portion of data based on the particular data descriptor and processes the particular portion of data in executing the task.

公开(公告)号：US20230084603A1

公开(公告)日：2023-03-16

申请号：US17474568

申请日：2021-09-14

Applicant: Arm Limited ,  Apical Limited

Inventor： Eric KUNZE ,  Jared Corey SMOLENS ,  Aaron DEBATTISTA ,  Elliot Maurice Simon ROSEMARINE

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/448 ,  G06F9/38

Abstract: Aspects of the present disclosure relate to apparatus comprising execution circuitry comprising at least one execution unit to execute program instructions, and control circuitry. The control circuitry receives a stream of processing instructions, and issues each received instruction to one of said at least one execution unit. Responsive to determining that a first type of context switch is to be performed from an initial context to a new context, issuing continues until a pre-emption point in the stream of processing instructions is reached. Responsive to reaching the pre-emption point, state information is stored, and the new context is switched to. Responsive to determining that a context switch is to be performed to return from the new context to the initial context, the processing status is restored from the state information, and the stream of processing instructions is continued.

公开(公告)号：US20240248755A1

公开(公告)日：2024-07-25

申请号：US18099595

申请日：2023-01-20

Applicant: Arm Limited

Inventor： Rune HOLM ,  Jens OLSON ,  Jared Corey SMOLENS ,  Dominic Hugo SYMES ,  Elliot Maurice Simon ROSEMARINE

IPC: G06F9/48 ,  G06F9/355

CPC classification number: G06F9/4881 ,  G06F9/3555

Abstract: A processor comprising: a handling unit; a plurality of components each configured to execute a function. The handling unit can receive a task comprising operations on data in a coordinate space having N dimensions, receive a data structure describing execution of the task and comprising a partially ordered set of data items each associated with instructions usable by the plurality of components when executing the task, each data item is associated with a component among the plurality of components, each data item indicates dimensions of the coordinates space for which changes of coordinate causes the function of the associated component to execute, and dimensions of the coordinate space for which changes of coordinate causes the function of the associated component to store data ready to be used by another component. The handling unit iterates over the coordinate space and executes the task using the partially ordered set of data items.

公开(公告)号：US20240248754A1

公开(公告)日：2024-07-25

申请号：US18099594

申请日：2023-01-20

Applicant: Arm Limited

Inventor： Elliot Maurice Simon ROSEMARINE ,  Jared Corey SMOLENS ,  Rune HOLM ,  John Wakefield BROTHERS, III ,  Jens OLSON

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: A processor to generate position data indicative of a position within a compressed data stream, wherein, previously, in executing a task, data of the compressed data stream ending at the position has been read by the processor from storage storing the compressed data stream. After reading the data, the processor reads further data of the compressed data stream from the storage, in executing the task, the further data located beyond the position within the compressed data stream. After reading the further data, the processor reads, based on the position data, a portion of the compressed data stream from the storage, in executing the task, starting from the position within the compressed data stream. The processor decompresses the portion of the compressed data stream to generate decompressed data, in executing the task.

公开(公告)号：US20210304012A1

公开(公告)日：2021-09-30

申请号：US16834948

申请日：2020-03-30

Applicant: Arm Limited

Inventor： Erik PERSSON ,  Stefan Johannes FRID ,  Elliot Maurice Simon ROSEMARINE

IPC: G06N3/10 ,  G06N3/04

Abstract: A computer implemented method of storing and retrieving feature map data of a neural network the method comprising receiving a first portion of feature map data from local storage, selecting a first set of subportions of the first portion of feature map data, compressing the subportions to produce a first plurality of sections of compressed feature map data and instructing the storage of the sections into external storage. The method also comprises receiving a second plurality of sections of compressed feature map data from the external storage, decompressing the sections to produce a second set of subportions of the second portion of feature map data and storing the second portion of feature map data in local storage. The first and second sets of subportions each correspond to a predetermined format of subdivision and the method comprises selecting the predetermined format of subdivision from a plurality of predetermined formats of subdivision.

公开(公告)号：US20240248721A1

公开(公告)日：2024-07-25

申请号：US18414230

申请日：2024-01-16

Applicant: Arm Limited

Inventor： Rune HOLM ,  Alexander Eugene CHALFIN ,  Elliot Maurice Simon ROSEMARINE

IPC: G06F9/38

CPC classification number: G06F9/3838

Abstract: A method and apparatus for distributing operations for execution. Input data is received and is subdivided into portions, each comprising a first and second sub-portion. A first operation and a second operation are received. Dependencies between the first and second operations are identified. For each portion the first operation is issued for execution on the first sub-portion to produce a first output sub-portion, and completion is tracked. The first operation is issued for execution on the second sub-portion to produce a second output sub-portion. Depending upon satisfaction of the dependencies in respect of the first sub-portion, either the second operation to be executed on the first output sub-portion is issued, if the dependencies are met; or the second operation, to be executed on the first output sub-portion is stalled, if the dependencies are not met. This is repeated for each subsequent portion.

公开(公告)号：US20220365853A1

公开(公告)日：2022-11-17

申请号：US17807054

申请日：2022-06-15

Applicant: Arm Limited

Inventor： Andrew Brian Thomas HOPKINS ,  Graeme Leslie INGRAM ,  Elliot Maurice Simon ROSEMARINE ,  Antonio PRIORE

IPC: G06F11/14 ,  G06N3/04 ,  G06N3/08 ,  G06N3/063 ,  G06F9/48

Abstract: A method of performing fault detection during computations relating to a neural network comprising a first neural network layer and a second neural network layer in a data processing system, the method comprising: scheduling computations onto data processing resources for the execution of the first neural network layer and the second neural network layer, wherein the scheduling includes: for a given one of the first neural network layer and the second neural network layer, scheduling a respective given one of a first computation and a second computation as a non-duplicated computation, in which the given computation is at least initially scheduled to be performed only once during the execution of the given neural network layer; and for the other of the first and second neural network layers, scheduling the respective other of the first and second computations as a duplicated computation.

公开(公告)号：US20210012185A1

公开(公告)日：2021-01-14

申请号：US16508912

申请日：2019-07-11

Applicant: Arm Limited

Inventor： Elliot Maurice Simon ROSEMARINE

IPC: G06N3/063 ,  G06F9/30 ,  G06F13/16 ,  G06K9/62

Abstract: There is provided a neural processing unit (NPU), including a primary processing node containing primary control registers and processing circuitry configured to write control data to the primary control registers, and multiple secondary processing nodes each having respective secondary control registers and being configured to process data in accordance with control data stored by the respective secondary control registers. The NPU also includes a bus interface for transmitting data between the primary processing node and the plurality of secondary processing nodes. The primary processing node is configured to transmit first control data to a given secondary control register of each of the plurality of secondary processing nodes.

公开(公告)号：US20240311947A1

公开(公告)日：2024-09-19

申请号：US18184212

申请日：2023-03-15

Applicant: Arm Limited

Inventor： Rune HOLM ,  Elliot Maurice Simon ROSEMARINE

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: A processor, method and non-transitory computer-readable storage medium for handling data, by obtaining task data describing a task to be executed in the form of a plurality of operations on data, the task data further defining an operation space of said data, analyzing each of the operations to define transformation data comprising transformation instruction representing a transform into an associated operation-specific local spaces. In case transformation instructions to get to the operation-specific local space for an operation are producing less dimensions compared to the operation space, one or more operation-specific arguments are stored in a data field corresponding to a dimension not produced by the transformation instructions in the transformation data corresponding to the operation.

公开(公告)号：US20240248764A1

公开(公告)日：2024-07-25

申请号：US18316602

申请日：2023-05-12

Applicant: Arm Limited

Inventor： Rune HOLM ,  Jens OLSON ,  Elliot Maurice Simon ROSEMARINE ,  Jared SMOLENS

IPC: G06F9/50

CPC classification number: G06F9/5038 ,  G06F9/505 ,  G06F2209/5021

Abstract: A memory unit configured for handling task data, the task data describing a task to be executed as a directed acyclic graph of operations, wherein each operation maps to a corresponding execution unit, and wherein each connection between operations in the acyclic graph maps to a corresponding storage element of the execution unit. The task data defines an operation space representing the dimensions of a multi-dimensional arrangement of the connected operations to be executed represented by the data blocks; the memory unit configured to receive a sequence of processing requests comprising the one or more data blocks with each data block assigned a priority value and comprising a block command. The memory unit is configured to arbitrate between the data blocks based upon the priority value and block command to prioritize the sequence of processing requests and wherein the processing requests include writing data to, or reading data from storage.