公开(公告)号：US20240078035A1

公开(公告)日：2024-03-07

申请号：US17900975

申请日：2022-09-01

Applicant: Arm Limited

Inventor： Xiaoyang SHEN ,  Zichao XIE ,  Leonardo INTESA

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: An apparatus has processing circuitry with one or more execution units to perform operations in response to instructions. The apparatus also has registers to store data accessed by the processing circuitry and forwarding circuitry to forward results of the operations from the execution units to be written back to the registers and to the execution units for use as operands of further operations. The apparatus also has write-back reschedule circuitry which for each operation causes an execution unit performing the operation to stall the operation prior to a write-back stage of the execution unit and determine, based on monitoring subsequent operations whether to forward the result of the operation to be written back to a register or to forward the result to an execution unit. The write-back reschedule circuitry also controls the forwarding circuitry to forward the result according to the determination.