公开(公告)号：US20240289130A1

公开(公告)日：2024-08-29

申请号：US18174207

申请日：2023-02-24

Applicant: Arm Limited

Inventor： Xiaoyang SHEN ,  Zichao XIE ,  Cédric Denis Robert AIRAUD ,  Grégorie MARTIN

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30098 ,  G06F9/3826 ,  G06F9/3869

Abstract: A data processing apparatus comprises operand routing circuitry configured to prepare operands for processing, and a plurality of processing elements. Each processing element comprises receiving circuitry, processing circuitry, and transmitting circuitry. A group of coupled processing elements comprises a first processing element configured to receive operands from the operand routing circuitry and one or more further processing elements for which the receiving circuitry is coupled to the transmitting circuitry of another processing element in the group. The apparatus also comprises timing circuitry, configured to selectively delay transmission of operands within the group of coupled processing elements to cause operations performed by the group of coupled processing elements to be staggered.

公开(公告)号：US20200371749A1

公开(公告)日：2020-11-26

申请号：US16417866

申请日：2019-05-21

Applicant: Arm Limited

Inventor： Michael Alexander KENNEDY ,  Neil BURGESS ,  Zichao XIE ,  Chiloda Ashan Senarath PATHIRANE

IPC: G06F7/53 ,  G06F7/509

Abstract: A multiplier circuit is described in which sub-products calculated in a first stage of a carry-save adder (CSA) network are output early, processed by applying a processing function, and re-injected into a subsequent stage of the CSA network to add the processed sub-products. This allows a CSA network provided for multiplication operations to be reused for operations which require sub-products to be processed and added, such as floating-point dot product operations performed on floating-point values represented in bfloatl6 format.

公开(公告)号：US20240086198A1

公开(公告)日：2024-03-14

申请号：US17943407

申请日：2022-09-13

Applicant: Arm Limited

Inventor： Xiaoyang SHEN ,  Zichao XIE

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/30123

Abstract: An apparatus has processing circuitry with execution units to perform operations, physical registers to store data, and forwarding circuitry to forward the data from the physical registers to the execution units. The forwarding circuitry provides an incomplete set of connections between the physical registers and the execution units such that, for each of at least some of the physical registers, the physical register is connected to only a subset of the execution units. The apparatus also has register renaming circuitry to map logical registers identified by the operations to respective physical registers and register reorganisation circuitry to monitor upcoming operations and to determine, based on the upcoming operations and the connections provided by the forwarding circuitry, whether to perform a register reorganisation procedure to change a mapping between the logical registers and the physical registers. The register reorganisation circuitry is also configured to perform the register reorganisation procedure.

公开(公告)号：US20240078035A1

公开(公告)日：2024-03-07

申请号：US17900975

申请日：2022-09-01

Applicant: Arm Limited

Inventor： Xiaoyang SHEN ,  Zichao XIE ,  Leonardo INTESA

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: An apparatus has processing circuitry with one or more execution units to perform operations in response to instructions. The apparatus also has registers to store data accessed by the processing circuitry and forwarding circuitry to forward results of the operations from the execution units to be written back to the registers and to the execution units for use as operands of further operations. The apparatus also has write-back reschedule circuitry which for each operation causes an execution unit performing the operation to stall the operation prior to a write-back stage of the execution unit and determine, based on monitoring subsequent operations whether to forward the result of the operation to be written back to a register or to forward the result to an execution unit. The write-back reschedule circuitry also controls the forwarding circuitry to forward the result according to the determination.

公开(公告)号：US20200057609A1

公开(公告)日：2020-02-20

申请号：US16105066

申请日：2018-08-20

Applicant: Arm Limited

Inventor： Michael Alexander KENNEDY ,  Neil BURGESS ,  Zichao XIE ,  Karel Hubertus Gerardus WALTERS

IPC: G06F7/523 ,  G06F15/80 ,  G06F9/38

Abstract: A configurable SIMD multiplication circuit is provided to perform multiplication on a multiplicand operand M and multiplier operand R with varying data element sizes supported. For each result element generated based on corresponding elements of the multiplicand operand M and the multiplier operand R, the multiplication is performed according to radix-N modified Booth multiplication, where N=2P and P≥3. A Booth digit selection scheme is described for improving the efficiency with which higher radix modified Booth multiplication can be implemented in a configurable SIMD multiplier.