公开(公告)号：US12222826B2

公开(公告)日：2025-02-11

申请号：US18104458

申请日：2023-02-01

Applicant: Arm Limited

Inventor： Ashok Kumar Tummala ,  FNU Parshant ,  Rishabh Jain ,  Apurva Patel ,  Surabhi Garg ,  Sai Kumar Marri

IPC: G06F11/07 ,  G06F11/20

Abstract: A mechanism for error containment in a data processing system includes receiving a transaction request at a gateway between a host and a device, allocating an entry for the request in a local request tracker of the gateway and sending a link request, to a port of the gateway. In response to an isolation trigger, the port is moved into isolation by completing in-process requests with entries in the tracker and locking the entries. On receiving a response to an in-process request while the port is in isolation, the response is dropped, the associated entry is unlocked, and allocation of the entry is enabled. A completion response is sent to the requester without dispatching a new link request to the port. When requests are completed, the system is quiesced, locked entries are unlocked, and the port is moved out of isolation.

公开(公告)号：US20240256406A1

公开(公告)日：2024-08-01

申请号：US18104458

申请日：2023-02-01

Applicant: Arm Limited

Inventor： Ashok Kumar Tummala ,  FNU Parshant ,  Rishabh Jain ,  Apurva Patel ,  Surabhi Garg ,  Sai Kumar Marri

IPC: G06F11/20

CPC classification number: G06F11/2007 ,  G06F11/203 ,  G06F2201/805

Abstract: A mechanism for error containment in a data processing system includes receiving a transaction request at a gateway between a host and a device, allocating an entry for the request in a local request tracker of the gateway and sending a link request, to a port of the gateway. In response to an isolation trigger, the port is moved into isolation by completing in-process requests with entries in the tracker and locking the entries. On receiving a response to an in-process request while the port is in isolation, the response is dropped, the associated entry is unlocked, and allocation of the entry is enabled. A completion response is sent to the requester without dispatching a new link request to the port. When requests are completed, the system is quiesced, locked entries are unlocked, and the port is moved out of isolation.

公开(公告)号：US11573918B1

公开(公告)日：2023-02-07

申请号：US17380112

申请日：2021-07-20

Applicant: Arm Limited

Inventor： Mark David Werkheiser ,  Sai Kumar Marri ,  Lauren Elise Guckert ,  Gurunath Ramagiri ,  Jamshed Jalal

IPC: G06F13/14 ,  G06F13/40

Abstract: Aspects of the present disclosure relate to an interconnect comprising interfaces to communicate with respective requester and receiver node devices, and home nodes. Each home node is configured to: receive requests from one or more requester nodes, each request comprising a target address corresponding to a target receiver nodes; and transmit each said request to the corresponding target receiver node. Mapping circuitry is configured to: associate each of said plurality of home nodes with a given home node cluster; perform a first hashing of the target address of a given request, to determine a target cluster; perform a second hashing of the target address, to determine a target home node within said target cluster; and direct the given message, to the target home node.

公开(公告)号：US11934334B2

公开(公告)日：2024-03-19

申请号：US17244182

申请日：2021-04-29

Applicant: Arm Limited

Inventor： Tushar P Ringe ,  Mark David Werkheiser ,  Jamshed Jalal ,  Sai Kumar Marri ,  Ashok Kumar Tummala ,  Rishabh Jain

IPC: G06F13/20 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4221 ,  G06F13/4068 ,  G06F13/4027 ,  G06F2213/0026

Abstract: The present disclosure advantageously provides a method and system for transferring data over a chip-to-chip interconnect (CCI). At a request node of a coherent interconnect (CHI) of a first chip, receiving at least one peripheral component interface express (PCIe) transaction from a PCIe master device, the PCIe transaction including a stream identifier; selecting a CCI port of the CHI of the first chip based on the stream identifier of the PCIe transaction; and sending the PCIe transaction to the selected CCI port.

公开(公告)号：US20220350771A1

公开(公告)日：2022-11-03

申请号：US17244182

申请日：2021-04-29

Applicant: Arm Limited

Inventor： Tushar P Ringe ,  Mark David Werkheiser ,  Jamshed Jalal ,  Sai Kumar Marri ,  Ashok Kumar Tummala ,  Rishabh Jain

IPC: G06F13/42 ,  G06F13/40

Abstract: The present disclosure advantageously provides a method and system for transferring data over a chip-to-chip interconnect (CCI). At a request node of a coherent interconnect (CHI) of a first chip, receiving at least one peripheral component interface express (PCIe) transaction from a PCIe master device, the PCIe transaction including a stream identifier; selecting a CCI port of the CHI of the first chip based on the stream identifier of the PCIe transaction; and sending the PCIe transaction to the selected CCI port.