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    END-TO-END ISOLATION OVER PCIE
    1.
    发明公开
    END-TO-END ISOLATION OVER PCIE 审中-公开

    公开(公告)号：US20240354272A1

    公开(公告)日：2024-10-24

    申请号：US18763195

    申请日：2024-07-03

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY

    IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F21/45

    CPC classification number: G06F13/4027 ,  G06F13/1668 ,  G06F13/4282 ,  G06F21/45 ,  G06F2213/0026

    Abstract: Examples systems are provided for isolating transactions originating from different types of applications, including systems for providing such isolation on an inbound side and systems for providing such isolation on an outbound side, as well as end-to-end isolation systems. Such systems may be implemented in a peripheral component interconnect express (PCIe) environment. On an outbound side, a first interconnect receives transactions having different attributes indicating different application origins, respectively, and selects different pathways for the transactions based on their respective attributes. On an inbound side, a second interconnect selects different pathways for the transactions based on their respective attributes. Thus, transactions originating from safety and non-safety applications may be kept isolated as they are routed, and a non-safety transaction may be restricted from accessing certain portions of memory.

    METHOD, CIRCUIT AND APPARATUS FOR PROTECTING POWER SUPPLY OF PCIE CARD, AND MEDIUM
    4.
    发明公开
    METHOD, CIRCUIT AND APPARATUS FOR PROTECTING POWER SUPPLY OF PCIE CARD, AND MEDIUM 审中-公开

    公开(公告)号：US20240329708A1

    公开(公告)日：2024-10-03

    申请号：US18697441

    申请日：2022-06-28

    Applicant: SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD.

    Inventor： Sanxia CHEN ,  Tiejun LIU ,  Jing JI

    IPC: G06F1/28 ,  G06F1/26 ,  G06F13/40 ,  H01L27/02

    CPC classification number: G06F1/28 ,  G06F1/266 ,  G06F13/4068 ,  H01L27/0266 ,  G06F2213/0026

    Abstract: A method, circuit and apparatus for protecting power supply of a peripheral component interconnect express (PCIE) card, and a medium are provided, card hardware design. When the PCIE card is not completely inserted into a slot of a server, a first power supply and a second power supply are controlled to release electric energy, a controller is controlled; to turn off a first MOS transistor, and a load is charged with the electric energy released by the second power supply. When the PCIE card is completely inserted into the slot of the server, a PRSNT #signal is generated, a second MOS transistor is controlled to be turned on, and the controller is controlled to turn on the first MOS transistor. When the PCIE card is not completely pulled out, the second MOS transistor is controlled to be turned off, and the controller is controlled to turn off the first MOS transistor.

    Synchronizing systems on a chip using a shared clock
    5.
    发明授权
    Synchronizing systems on a chip using a shared clock 有权

    公开(公告)号：US12105553B2

    公开(公告)日：2024-10-01

    申请号：US18236732

    申请日：2023-08-22

    Applicant: Snap Inc.

    Inventor： Samuel Ahn ,  Jason Heger ,  Dmitry Ryuma

    IPC: G06F1/12 ,  G06F1/04 ,  G06F1/14 ,  G06F1/16 ,  G06F3/01 ,  G06F13/42 ,  G06F15/173

    CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F1/14 ,  G06F1/163 ,  G06F3/011 ,  G06F13/4221 ,  G06F15/17325 ,  G06F2213/0026

    Abstract: An electronic eyewear device includes first and second systems on a chip (SoCs) having independent time bases that are synchronized by generating a common clock signal from a clock generator of the first SoC and simultaneously applying the common clock signal to a first counter of the first SoC and a second counter of the second SoC whereby the first counter and the second counter count clock edges of the common clock. The clock counts are shared through an interface between the first SoC and the second SoC and compared to each other. When the clock counts are different, a clock count of the first counter or the second counter is adjusted to cause the clock counts to match each other. The adjusted clock count is synchronized to the respective clocks of the first and second SoCs, thus synchronizing the first and second SoCs to each other.

    Multiple port emulation
    8.
    发明授权
    Multiple port emulation 有权

    公开(公告)号：US12093706B2

    公开(公告)日：2024-09-17

    申请号：US18186748

    申请日：2023-03-20

    Applicant: Amazon Technologies, Inc.

    Inventor： Barak Wasserstrom ,  Said Bshara ,  Akram Baransi ,  Omri Itach ,  Tal Zilcer

    IPC: G06F9/455 ,  G06F13/10 ,  G06F13/24 ,  G06F13/42

    CPC classification number: G06F9/455 ,  G06F13/105 ,  G06F13/24 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026

    Abstract: Multiple independent endpoint devices can be emulated using a single system on chip (SoC) device. Such a SoC can have multiple cores that can emulate ports according to a specified protocol, such as the peripheral component interconnect express (PCIe) protocol useful for data communications. An emulation agent can manage various aspects of these emulated endpoint devices in software, including serving interrupts for relevant emulated devices according to a determined priority scheme. Interrupts can be registered for each device, and data structures allocated dynamically for a determined number and type(s) of PCIe endpoint devices to be emulated. Each PCIe core on the SoC can function as a separate PCIe endpoint device endpoint for communicating with one or more hosts or other such devices.

    Techniques for testing semiconductor devices
    9.
    发明授权
    Techniques for testing semiconductor devices 有权

    公开(公告)号：US12079097B2

    公开(公告)日：2024-09-03

    申请号：US17075628

    申请日：2020-10-20

    Applicant: NVIDIA CORPORATION

    Inventor： Animesh Khare ,  Ashish Kumar ,  Shantanu Sarangi ,  Rahul Garg

    IPC: G06F11/273 ,  G06F11/22 ,  G06F13/28 ,  G06F13/42

    CPC classification number: G06F11/2733 ,  G06F11/2268 ,  G06F13/28 ,  G06F13/4282 ,  G06F2213/0026

    Abstract: Techniques for testing semiconductor devices include a semiconductor device having a plurality of components, a test bus, and a test data transfer unit. The test data transfer unit receives, from a host computer, configuration information for performing a test of the semiconductor device, reads, via a high-speed data transfer link, test data associated with the test from memory of the host computer using direct memory access, sends the test data to the plurality of components via the test bus, causes one or more operations to be performed on the semiconductor device to effect at least a portion of the test, and after the one or more operations have completed, retrieves test results of the at least a portion of the test from the test bus and stores, via the high-speed data transfer link, the test results in the memory of the host computer using direct memory access.

    DATA OPERATION SYSTEM, DATA OPERATION METHOD, AND STORAGE MEDIUM
    10.
    发明公开
    DATA OPERATION SYSTEM, DATA OPERATION METHOD, AND STORAGE MEDIUM 审中-公开

    公开(公告)号：US20240273048A1

    公开(公告)日：2024-08-15

    申请号：US18442637

    申请日：2024-02-15

    Applicant: Alibaba (China) Co., Ltd.

    Inventor： Linyong HUANG ,  Zhe ZHANG ,  Shuangchen LI ,  Hongzhong ZHENG

    IPC: G06F13/40

    CPC classification number: G06F13/4045 ,  G06F13/4022 ,  G06F2213/0026

    Abstract: A data operation system includes: a plurality of data processing units; a memory expansion unit communicatively coupled to the plurality of data processing units; a plurality of data operation units communicatively coupled to the plurality of data processing units and the memory expansion unit; and a plurality of first storage units communicatively coupled to the plurality of data processing units; wherein the memory expansion unit comprises a plurality of memory expansion cards, each of the plurality of data processing units is communicatively coupled to at least one of the plurality of memory expansion cards, and the plurality of memory expansion cards are interconnected.

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