Abstract:
A simple, fast, low-power-consumption full adder, suitable for fabrication in integrated circuit form, includes in each stage thereof two identical exclusive-NOR circuits and a three-input variation of the exclusive-NOR circuit.
Abstract:
Shift register circuitry is disclosed in which bidirectional gates are connected between register stages in such a manner that data may be shifted in either direction through a gate to alter the state of either interconnected stage. By use of the bidirectional gates the shift register circuitry can store the logical AND or OR of the contents of the interconnected stages without employing additional complex control or steering circuitry intermediate the register stages. The shift register circuitry can also be used in various data processing shift and rotate functions in which a second register acts as intermediary for the shifting or rotation of data through a first register.
Abstract:
In a time division switching system, speech samples from a subscriber station are first encoded and then stored, in digital coded form in a register in a transceiver. The output of this register is gated to a second register in the common talking bus or highway during a first portion of a time slot; the sample from this register in the common highway is gated in a later portion of the same time slot to a similar transceiver connected to the called subscriber. It is then subsequently decoded and applied to the called subscriber. Two-wire, four-wire, and conferencing arrangements are disclosed.