Abstract:
An information processing system characterized by modularity of design and good maintenance features includes a plurality of oneout-of-N translators each of which includes double-output detection circuitry. Some of the translators are operated in a conventional manner to convert a multidigit input word into energization of one particular one of N output lines emanating therefrom. Others of the translators are supplied with periodic clock signals, steady-state reference signals and instruction signals. In response to such a set of signals, these other translators are operated in a unique manner to provide a specified plurality of sequential control signals which are applied to a matrix array to cause the readout therefrom of a corresponding plurality of stored words.
Abstract:
A parallel counter using noncomplementing bistable circuits has coincidence gates associated with the bistable circuits to detect the lowest ordered counter stage in a reset state at the time of a counter input pulse. The gates are operative to set that counter stage and to reset all lower ordered stages. By using gates with different degrees of fan-in, the amount of delay in each counting operation can be correspondingly changed to produce a similar change in the input pulse repetition frequency that can be accommodated by the counter.
Abstract:
Shift register circuitry is disclosed in which bidirectional gates are connected between register stages in such a manner that data may be shifted in either direction through a gate to alter the state of either interconnected stage. By use of the bidirectional gates the shift register circuitry can store the logical AND or OR of the contents of the interconnected stages without employing additional complex control or steering circuitry intermediate the register stages. The shift register circuitry can also be used in various data processing shift and rotate functions in which a second register acts as intermediary for the shifting or rotation of data through a first register.
Abstract:
In a time division switching system, speech samples from a subscriber station are first encoded and then stored, in digital coded form in a register in a transceiver. The output of this register is gated to a second register in the common talking bus or highway during a first portion of a time slot; the sample from this register in the common highway is gated in a later portion of the same time slot to a similar transceiver connected to the called subscriber. It is then subsequently decoded and applied to the called subscriber. Two-wire, four-wire, and conferencing arrangements are disclosed.
Abstract:
The first instruction in a program loop and the address of the second instruction in the loop are temporarily stored in a small, fast, secondary memory. These temporarily stored values are then used each time the last instruction in the loop transfers to the first instruction, thereby saving n-l primary memory fetches in a loop executed n times.