公开(公告)号：US20210268505A1

公开(公告)日：2021-09-02

申请号：US17256077

申请日：2020-06-03

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Qingzhao LIU ,  Shuilang DONG

IPC: B01L3/00 ,  G01N21/59

Abstract: The present disclosure provides a microfluidic substrate, a microfluidic chip and a micro total analysis system. The microfluidic substrate includes a substrate and an ultrasonic structure on the substrate. The ultrasonic structure is configured to generate ultrasonic waves during a droplet splitting process to vibrate a droplet.

公开(公告)号：US20210333457A1

公开(公告)日：2021-10-28

申请号：US16485810

申请日：2019-01-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Shuilang DONG ,  Xin GU ,  Kang GUO ,  Da LU ,  Qingzhao LIU ,  Lei ZHAO

IPC: G02B5/30 ,  C23F1/12 ,  G03F7/16 ,  G03F7/42 ,  G03F7/00

Abstract: A method of manufacturing a metal wire, a method of manufacturing a metal wire grid, a wire grid polarizer, and an electronic device are provided. The method of manufacturing a metal wire includes: forming a metal material layer on a base substrate etching the metal material layer by using a composite gas including an etching gas and a coating reaction gas to form the metal wire and a protective coating layer on a surface of the metal wire.

公开(公告)号：US20210226079A1

公开(公告)日：2021-07-22

申请号：US16763178

申请日：2019-12-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guoqiang WANG ,  Jiushi WANG ,  Qingzhao LIU

IPC: H01L31/105 ,  H01L31/115 ,  H01L31/18

Abstract: A PIN device includes: a first doped layer, a second doped layer, and an intrinsic layer between the first doped layer and the second doped layer, where the second doped layer includes a body portion and an electric field isolating portion at least partially enclosing the body portion; and the electric field isolating portion is doped differently from the body portion.

公开(公告)号：US20200166683A1

公开(公告)日：2020-05-28

申请号：US16408973

申请日：2019-05-10

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Qingzhao LIU ,  Jiushi WANG ,  Shuilang DONG ,  Guoqiang WANG

IPC: G02B5/30 ,  G02B5/02

Abstract: An embodiment of this disclosure discloses a metal wire grid comprising: a patterned metal layer and a patterned antireflective layer located on the patterned metal layer, wherein a surface of the antireflective layer distal to the patterned metal layer has a plurality of continuous pits. Embodiments of this disclosure further disclose a method of manufacturing a metal wire grid and a display panel.

公开(公告)号：US20190080928A1

公开(公告)日：2019-03-14

申请号：US16108185

申请日：2018-08-22

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Qingzhao LIU ,  Jiushi WANG ,  Lei ZHAO

IPC: H01L21/3213 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A dry etching method, including: etching a silicon-containing thin film with a first gas by a first preset thickness; etching the silicon-containing thin film with a second gas by a second preset thickness, to remove etching residues generated after etching the silicon-containing thin film by the first preset thickness; after the etching residues are removed, etching the silicon-containing thin film with the first gas by a third preset thickness, which is less than the first preset thickness; wherein the first gas includes chlorine gas, and the second gas includes fluoride gas.