公开(公告)号：US20210249403A1

公开(公告)日：2021-08-12

申请号：US17267835

申请日：2019-08-15

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/866

Abstract: A transient voltage suppression device and a manufacturing method therefor, the transient voltage suppression device including: a substrate, a first conductivity type well region and a second conductivity type well region disposed in the substrate. The first conductivity type well region includes a first well, a second well, and a third well. The second conductivity type well region includes a fourth well that isolates the first well from the second well, and a fifth well that isolates the second well from the third well. The device further includes a Zener diode well region provided in the first well, a first doped region provided in the Zener diode well region, a second doped region provided in the Zener diode well region, a third doped region provided in the second well, a fourth doped region provided in the third well, and a fifth doped region provided in the third well.

公开(公告)号：US11887979B2

公开(公告)日：2024-01-30

申请号：US17267835

申请日：2019-08-15

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/866

CPC classification number: H01L27/0255 ,  H01L27/0262 ,  H01L27/0296 ,  H01L29/66106 ,  H01L29/866

Abstract: A transient voltage suppression device and a manufacturing method therefor, the transient voltage suppression device including: a substrate, a first conductivity type well region and a second conductivity type well region disposed in the substrate. The first conductivity type well region includes a first well, a second well, and a third well. The second conductivity type well region includes a fourth well that isolates the first well from the second well, and a fifth well that isolates the second well from the third well. The device further includes a Zener diode well region provided in the first well, a first doped region provided in the Zener diode well region, a second doped region provided in the Zener diode well region, a third doped region provided in the second well, a fourth doped region provided in the third well, and a fifth doped region provided in the third well.

公开(公告)号：US11387349B2

公开(公告)日：2022-07-12

申请号：US17265587

申请日：2019-10-14

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan Gu ,  Shikang Cheng ,  Sen Zhang

IPC: H01L29/66 ,  H01L29/78

Abstract: A trench gate depletion-type VDMOS device and a method for manufacturing the same are disclosed. The device comprises a drain region; a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer; a channel region located around the gate insulating layer; a well region located on both sides of the trench gate; a source regions located within the well region; a drift region located between the well region and the drain region; a second conductive-type doped region located between the channel region and the drain region; and a first conductive-type doped region located on both sides of the second conductive-type doped region and located between the drift region and the drain region.

公开(公告)号：US11276690B2

公开(公告)日：2022-03-15

申请号：US16755817

申请日：2018-11-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/088 ,  H01L29/78

Abstract: The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.

公开(公告)号：US20230122120A1

公开(公告)日：2023-04-20

申请号：US17265549

申请日：2019-08-15

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/866 ,  H01L29/66 ,  H01L29/06

Abstract: A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.

公开(公告)号：US11430780B2

公开(公告)日：2022-08-30

申请号：US17266134

申请日：2019-11-01

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L21/266 ,  H01L29/06 ,  H01L29/74 ,  H01L29/866

Abstract: A TVS device and a manufacturing method therefor. The TVS device comprises: a first doping type semiconductor substrate (100); a second doping type deep well I (101), a second doping type deep well II (102), and a first doping type deep well (103) provided on the semiconductor substrate; a second doping type heavily doped region I (104) provided in the second doping type deep well I (101); a first doping type well region (105) and a first doping type heavily doped region I (106) provided in the second doping type deep well II (102); a first doping type heavily doped region II (107) and a second doping type heavily doped region II (108) provided in the first doping type deep well (105); a second doping type heavily doped region III (109) located in the first doping type well region (105) and the second doping type deep well II (102); and a first doping type doped region (110) provided in the first doping type well region (105).

公开(公告)号：US11257720B2

公开(公告)日：2022-02-22

申请号：US16768563

申请日：2018-11-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/266

Abstract: A manufacturing method for a semiconductor device, and an integrated semiconductor device. The manufacturing method comprises: on a semiconductor substrate, forming an epitaxial layer having a first region, a second region, and a third region; forming at least one groove in the third region, forming at least two second doping deep traps in the first region, and forming at least two second doping deep traps in the second region; forming a first dielectric island between the second doping deep traps and forming a second dielectric island on the second doping deep traps; forming a first doping groove at both sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; forming an isolated first doping source region using the second dielectric island as a mask.

公开(公告)号：US11233045B2

公开(公告)日：2022-01-25

申请号：US17265541

申请日：2019-09-04

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/866

Abstract: A transient voltage suppression device includes a substrate; a first conductivity type well region disposed in the substrate and comprising a first well and a second well; a third well disposed on the substrate, a bottom part of the third well extending to the substrate; a fourth well disposed in the first well; a first doped region disposed in the second well; a second doped region disposed in the third well; a third doped region disposed in the fourth well; a fourth doped region disposed in the fourth well; a fifth doped region extending from inside of the fourth well to the outside of the fourth well, a portion located outside the fourth well being located in the first well; a sixth doped region disposed in the first well; a seventh doped region disposed below the fifth doped region and in the first well.

公开(公告)号：US12015025B2

公开(公告)日：2024-06-18

申请号：US17265549

申请日：2019-08-15

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/866

CPC classification number: H01L27/0255 ,  H01L29/0692 ,  H01L29/66106 ,  H01L29/866

Abstract: A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.

公开(公告)号：US20210358903A1

公开(公告)日：2021-11-18

申请号：US17266134

申请日：2019-11-01

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/866 ,  H01L29/74 ,  H01L21/266

Abstract: A TVS device and a manufacturing method therefor. The TVS device comprises: a first doping type semiconductor substrate (100); a second doping type deep well I (101), a second doping type deep well II (102), and a first doping type deep well (103) provided on the semiconductor substrate; a second doping type heavily doped region I (104) provided in the second doping type deep well I (101); a first doping type well region (105) and a first doping type heavily doped region I (106) provided in the second doping type deep well II (102); a first doping type heavily doped region II (107) and a second doping type heavily doped region II (108) provided in the first doping type deep well (105); a second doping type heavily doped region III (109) located in the first doping type well region (105) and the second doping type deep well II (102); and a first doping type doped region (110) provided in the first doping type well region (105).