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公开(公告)号：US20150354945A1
公开(公告)日：2015-12-10
申请号：US14762837
申请日：2013-12-31
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Wei Huang
CPC classification number: G03F7/70625 , G01B11/02 , H01L22/12 , H01L23/544
Abstract: A testing structure of a strip width of a scribing slot is provided, the structure includes a first isolated line (232) and a second isolated line (234) which are perpendicular to each other, the testing structure further includes a first field region pattern (220), the first field region pattern (220) includes two graphics, the two graphics are each located on one side of the first isolated line (232) and opposite to each other. A testing method of a strip width of a scribing slot is also disclosed. Graphics of the field oxide region simulating the LOCOS structure are provided on two sides of the isolated line, the step is artificially generated, a polysilicon gate graphic on a small size source region formed by photolithography can be displayed through online testing of the strip width or online displaying and checking of the strip width, thus a practical situation of the die can be known, an abnormity of the strip width and morphology of the polysilicon gate caused by a reflection of a substrate can be found instantly.
Abstract translation: 提供了划线槽的带宽的测试结构，该结构包括彼此垂直的第一隔离线（232）和第二隔离线（234），测试结构还包括第一场区域图案 220），第一场区域图案（220）包括两个图形，两个图形各自位于第一隔离线（232）的一侧并且彼此相对。 还公开了划线槽的带宽的测试方法。 模拟LOCOS结构的场氧化物区域的图形被提供在隔离线的两侧，人造地生成步骤，通过光刻形成的小尺寸源区域上的多晶硅栅极图形可以通过在线测试带宽或 在线显示和检查条带宽度，因此可以知道模具的实际情况，可以立即发现由基板的反射引起的多晶硅栅极的宽度和形态异常。
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公开(公告)号：US09778577B2
公开(公告)日：2017-10-03
申请号：US14762837
申请日：2013-12-31
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Wei Huang
IPC: G03F7/20 , H01L23/544 , G01B11/02 , H01L21/66
CPC classification number: G03F7/70625 , G01B11/02 , H01L22/12 , H01L23/544
Abstract: A testing structure of a strip width of a scribing slot is provided, the structure includes a first isolated line (232) and a second isolated line (234) which are perpendicular to each other, the testing structure further includes a first field region pattern (220), the first field region pattern (220) includes two graphics, the two graphics are each located on one side of the first isolated line (232) and opposite to each other. A testing method of a strip width of a scribing slot is also disclosed. Graphics of the field oxide region simulating the LOCOS structure are provided on two sides of the isolated line, the step is artificially generated, a polysilicon gate graphic on a small size source region formed by photolithography can be displayed through online testing of the strip width or online displaying and checking of the strip width, thus a practical situation of the die can be known, an abnormity of the strip width and morphology of the polysilicon gate caused by a reflection of a substrate can be found instantly.
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