公开(公告)号：US20240282621A1

公开(公告)日：2024-08-22

申请号：US18571601

申请日：2022-06-17

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Wenwen ZHANG ,  Renrui HUANG ,  Yongzhi FANG

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522

CPC classification number: H01L21/7681 ,  H01L21/31116 ,  H01L21/76877 ,  H01L23/5226

Abstract: A manufacturing method for a semiconductor device includes: forming an etching termination layer, a first dielectric layer, an auxiliary dielectric layer and a second dielectric layer which are successively stacked from bottom to top; by taking a photoresist layer as an etching barrier layer, patterning the second dielectric layer to obtain a first opening pattern, the bottom of the first opening being provided with a second opening pattern exposing part of the auxiliary dielectric layer; forming a first trench passing through the second dielectric layer and the auxiliary dielectric layer and extending to the first dielectric layer, and forming a second trench passing through the first dielectric layer from the bottom of the first trench and extending to the etching termination layer; and forming a conductive layer in the first and second trenches.