MEMORY DEVICE CAPABLE OF SUPPORTING SEQUENTIAL MULTIPLE-BYTE READING
    1.
    发明申请
    MEMORY DEVICE CAPABLE OF SUPPORTING SEQUENTIAL MULTIPLE-BYTE READING 审中-公开
    支持顺序多字节读取的记忆设备

    公开(公告)号:US20050125622A1

    公开(公告)日:2005-06-09

    申请号:US10709792

    申请日:2004-05-28

    CPC classification number: G11C7/106 G11C7/1018 G11C7/1051 G11C7/1069

    Abstract: When the memory device receives address information and byte information M, the memory device continuously provides M bytes corresponding to M addresses following an address assigned in the address information. The memory device includes: an address calculation module, an address buffer, a decoding module, a plurality of memory units and output buffers. Each output buffer is capable of receiving data of two units and sequentially outputting the data. When the address calculation module stores an address in the address buffer, the decoding module makes cells corresponding to the address simultaneously output data to the output buffers, such that the output buffers sequentially output data of respective unit. The address calculation module starts to count the next address, such that when the output buffer finishes outputting, the next address is already stored in the address buffer, and the decoding module has already made units corresponding to the next address output data.

    Abstract translation: 当存储装置接收到地址信息和字节信息M时,存储装置连续提供与在地址信息中分配的地址相对应的M个地址的M个字节。 存储装置包括:地址计算模块,地址缓冲器,解码模块,多个存储器单元和输出缓冲器。 每个输出缓冲器能够接收两个单元的数据并顺序输出数据。 当地址计算模块在地址缓冲器中存储地址时,解码模块使与地址相对应的单元同时输出数据到输出缓冲器,使得输出缓冲器顺序输出各单元的数据。 地址计算模块开始对下一个地址进行计数,使得当输出缓冲器完成输出时,下一个地址已经存储在地址缓冲器中,并且解码模块已经做出了与下一个地址输出数据相对应的单元。

    METHOD AND RELATED SYSTEM FOR ACCESSING LPC MEMORY OR FIRMWARE MEMORY IN A COMPUTER SYSTEM
    2.
    发明申请
    METHOD AND RELATED SYSTEM FOR ACCESSING LPC MEMORY OR FIRMWARE MEMORY IN A COMPUTER SYSTEM 审中-公开
    用于在计算机系统中访问LPC存储器或固件存储器的方法和相关系统

    公开(公告)号:US20050204089A1

    公开(公告)日:2005-09-15

    申请号:US10710016

    申请日:2004-06-13

    CPC classification number: G06F13/1657

    Abstract: A method and related system for accessing low pin count (LPC) memory or firmware memory includes selecting an LPC memory or a firmware memory according to an input signal, recording an address of the selected memory, determining weather to read or write data according to the input signal, and accessing data accordingly.

    Abstract translation: 用于访问低引脚数(LPC)存储器或固件存储器的方法和相关系统包括根据输入信号选择LPC存储器或固件存储器,记录所选择的存储器的地址,根据所述存储器确定天气读取或写入数据 输入信号,并相应地访问数据。

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