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    Extended error detection for a memory device
    2.
    发明授权
    Extended error detection for a memory device 有权

    公开(公告)号：US11675662B2

    公开(公告)日：2023-06-13

    申请号：US17348211

    申请日：2021-06-15

    申请人： Micron Technology, Inc.

    发明人： Scott E. Schaefer ,  Jongtae Kwak ,  Aaron P. Boehm

    IPC分类号： G06F11/10 ,  G11C7/10

    CPC分类号： G06F11/1072 ,  G06F11/1012 ,  G06F11/1052 ,  G11C7/1018

    摘要： Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.

    LOW POWER MEMORY DEVICE
    6.
    发明申请
    LOW POWER MEMORY DEVICE 审中-公开

    公开(公告)号：US20170372758A1

    公开(公告)日：2017-12-28

    申请号：US15497229

    申请日：2017-04-26

    申请人： Chih-Cheng Hsiao

    发明人： Chih-Cheng Hsiao

    IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C8/14

    CPC分类号： G11C7/1006 ,  G11C7/1012 ,  G11C7/1018 ,  G11C8/12 ,  G11C8/14 ,  G11C11/418 ,  G11C11/419

    摘要： A memory device comprises a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit comprises a plurality of memory cells arranged along a second direction different from the first direction; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; and at least one column word line elongated along the second direction; wherein the memory cell comprises a storage cell configured to store data and at least two access transistors; wherein a control terminal of one of the at least two access transistors of the memory cell is coupled to the at least one column word line, and a control terminal of another one of the at least two access transistors of the memory cell is coupled to the corresponding word line.

    Dynamic burst length output control in a memory
    9.
    发明授权
    Dynamic burst length output control in a memory 有权
    内存中的动态突发长度输出控制

    公开(公告)号：US09373371B2

    公开(公告)日：2016-06-21

    申请号：US14530911

    申请日：2014-11-03

    申请人： Micron Technology, Inc.

    发明人： Jongtae Kwak

    IPC分类号： G11C7/10 ,  G11C7/22

    CPC分类号： G11C7/106 ,  G11C7/1018 ,  G11C7/1066 ,  G11C7/222

    摘要： A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by using substantially the same latency delayed received command indications. A downstream clock generation circuit generates a clock signal from a received command indication delayed by both a delay locked loop and latency delays stored in latency control circuits. An upstream clock generation circuit generates a clock signal from the received command indication delayed by the delay locked loop and capture indications from the latency control circuits.

    摘要翻译： 用于控制动态突发长度控制数据的存储器，系统和方法可以通过使用基本上相同的等待时间延迟的接收命令指示来为上游计数器和下游计数器产生时钟。 下行时钟产生电路从延迟锁定环路延迟的接收到的命令指示和等待时间控制电路中存储的等待时延延迟生成时钟信号。 上行时钟发生电路根据延迟锁定环延迟的接收命令指示产生时钟信号，并从等待时间控制电路捕获指示。