公开(公告)号：US20050204089A1

公开(公告)日：2005-09-15

申请号：US10710016

申请日：2004-06-13

Applicant: Chao-Ping Chuang ,  Jen-Chin Chan

Inventor： Chao-Ping Chuang ,  Jen-Chin Chan

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F13/1657

Abstract: A method and related system for accessing low pin count (LPC) memory or firmware memory includes selecting an LPC memory or a firmware memory according to an input signal, recording an address of the selected memory, determining weather to read or write data according to the input signal, and accessing data accordingly.

Abstract translation: 用于访问低引脚数（LPC）存储器或固件存储器的方法和相关系统包括根据输入信号选择LPC存储器或固件存储器，记录所选择的存储器的地址，根据所述存储器确定天气读取或写入数据 输入信号，并相应地访问数据。

公开(公告)号：US20050125622A1

公开(公告)日：2005-06-09

申请号：US10709792

申请日：2004-05-28

Applicant: Chao-Ping Chuang ,  Jen-Chin Chan

Inventor： Chao-Ping Chuang ,  Jen-Chin Chan

IPC: G06F12/04 ,  G11C7/10

CPC classification number: G11C7/106 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/1069

Abstract: When the memory device receives address information and byte information M, the memory device continuously provides M bytes corresponding to M addresses following an address assigned in the address information. The memory device includes: an address calculation module, an address buffer, a decoding module, a plurality of memory units and output buffers. Each output buffer is capable of receiving data of two units and sequentially outputting the data. When the address calculation module stores an address in the address buffer, the decoding module makes cells corresponding to the address simultaneously output data to the output buffers, such that the output buffers sequentially output data of respective unit. The address calculation module starts to count the next address, such that when the output buffer finishes outputting, the next address is already stored in the address buffer, and the decoding module has already made units corresponding to the next address output data.

Abstract translation: 当存储装置接收到地址信息和字节信息M时，存储装置连续提供与在地址信息中分配的地址相对应的M个地址的M个字节。 存储装置包括：地址计算模块，地址缓冲器，解码模块，多个存储器单元和输出缓冲器。 每个输出缓冲器能够接收两个单元的数据并顺序输出数据。 当地址计算模块在地址缓冲器中存储地址时，解码模块使与地址相对应的单元同时输出数据到输出缓冲器，使得输出缓冲器顺序输出各单元的数据。 地址计算模块开始对下一个地址进行计数，使得当输出缓冲器完成输出时，下一个地址已经存储在地址缓冲器中，并且解码模块已经做出了与下一个地址输出数据相对应的单元。

公开(公告)号：US20100149901A1

公开(公告)日：2010-06-17

申请号：US12336547

申请日：2008-12-17

Applicant: Jen-Chin Chan

Inventor： Jen-Chin Chan

IPC: G11C8/10 ,  G11C8/08

CPC classification number: G11C8/10 ,  G11C8/08

Abstract: A word line decoder circuit is provided in the present invention. The word line decoder circuit comprises at least one local pre-decoder, at least one 3-transistors row driver, a controllable power supply, and a controllable pull-down circuit. The controllable power supply is controlled by an inversed sector select signal to provide a first voltage to the row driver and local pre-decoder. The local pre-decoder uses 5-transistors architecture, in which there are 2 PMOS transistors and 3 NOS transistors. The controllable pull-down circuit pulls down the local pre-decoder and is controlled by a sector select signal and pre-decoding signal. The local pre-decoder receives a local pre-decoding signal to select the row driver. When the row driver is selected, the row driver determines a word line according to a row driver pull-down signal and a row driver pull-up signal.

Abstract translation: 在本发明中提供了字线解码电路。 字线解码器电路包括至少一个本地预解码器，至少一个3晶体管行驱动器，可控电源和可控下拉电路。 可控电源由反向扇区选择信号控制，以向行驱动器和本地预解码器提供第一电压。 本地预解码器使用5晶体管架构，其中有2个PMOS晶体管和3个NOS晶体管。 可控下拉电路拉低本地预解码器，并由扇区选择信号和预解码信号控制。 本地预解码器接收本地预解码信号以选择行驱动器。 当选择行驱动器时，行驱动器根据行驱动器下拉信号和行驱动器上拉信号来确定字线。

公开(公告)号：US07782705B2

公开(公告)日：2010-08-24

申请号：US12336547

申请日：2008-12-17

Applicant: Jen-Chin Chan

Inventor： Jen-Chin Chan

IPC: G11C8/00

CPC classification number: G11C8/10 ,  G11C8/08

Abstract: A word line decoder circuit is provided in the present invention. The word line decoder circuit comprises at least one local pre-decoder, at least one 3-transistors row driver, a controllable power supply, and a controllable pull-down circuit. The controllable power supply is controlled by an inversed sector select signal to provide a first voltage to the row driver and local pre-decoder. The local pre-decoder uses 5-transistors architecture, in which there are 2 PMOS transistors and 3 NOS transistors. The controllable pull-down circuit pulls down the local pre-decoder and is controlled by a sector select signal and pre-decoding signal. The local pre-decoder receives a local pre-decoding signal to select the row driver. When the row driver is selected, the row driver determines a word line according to a row driver pull-down signal and a row driver pull-up signal.

Abstract translation: 在本发明中提供了字线解码电路。 字线解码器电路包括至少一个本地预解码器，至少一个3晶体管行驱动器，可控电源和可控下拉电路。 可控电源由反向扇区选择信号控制，以向行驱动器和本地预解码器提供第一电压。 本地预解码器使用5晶体管架构，其中有2个PMOS晶体管和3个NOS晶体管。 可控下拉电路拉低本地预解码器，并由扇区选择信号和预解码信号控制。 本地预解码器接收本地预解码信号以选择行驱动器。 当选择行驱动器时，行驱动器根据行驱动器下拉信号和行驱动器上拉信号来确定字线。

公开(公告)号：US20100020629A1

公开(公告)日：2010-01-28

申请号：US12177885

申请日：2008-07-23

Applicant: Jen-Chin Chan

Inventor： Jen-Chin Chan

IPC: G11C8/08

CPC classification number: G11C8/08 ,  G11C8/10 ,  G11C8/14

Abstract: A sector of a word line driver circuit is provided, comprising a local reset signal generator module and m word line clusters. The m word line clusters are coupled to the local reset signal generator module. The local reset signal generator module is used to generate j reset signals. The x-th reset signal is determined according to an x-th pre-decoding signal, a bank selectable signal and a sector selectable signal, wherein j is a nature number, and x is an integer from 1 to j. Each of the m word line clusters comprises j row drivers. The x-th row driver of the y-th word line cluster determines a [x+j*(y−1)]-th word line signal according to the x-th reset signal, the x-th pre-decoding signal, the sector selectable signal, and a y-th cluster select signal, wherein m is a nature number, and y is an integer from 1 to m.

Abstract translation: 提供了一种字线驱动电路的扇区，包括本地复位信号发生器模块和m个字线簇。 m个字线簇耦合到本地复位信号发生器模块。 本地复位信号发生器模块用于产生j个复位信号。 根据第X预解码信号，存储体可选择信号和扇区可选择信号确定第x个复位信号，其中j是自然数，x是从1到j的整数。 每个m个字线簇包括j个行驱动器。 第y个字线簇的第x行驱动器根据第x个复位信号，第x个预解码信号确定一个[x + j *（y-1）]个字线信号， 扇区可选择信号和第y个群集选择信号，其中m是自然数，y是1至m的整数。

公开(公告)号：US07746721B2

公开(公告)日：2010-06-29

申请号：US12177885

申请日：2008-07-23

Applicant: Jen-Chin Chan

Inventor： Jen-Chin Chan

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G11C8/10 ,  G11C8/14

Abstract: A sector of a word line driver circuit is provided, comprising a local reset signal generator module and m word line clusters. The m word line clusters are coupled to the local reset signal generator module. The local reset signal generator module is used to generate j reset signals. The x-th reset signal is determined according to an x-th pre-decoding signal, a bank selectable signal and a sector selectable signal, wherein j is a nature number, and x is an integer from 1 to j. Each of the m word line clusters comprises j row drivers. The x-th row driver of the y-th word line cluster determines a [x+j*(y−1)]-th word line signal according to the x-th reset signal, the x-th pre-decoding signal, the sector selectable signal, and a y-th cluster select signal, wherein m is a nature number, and y is an integer from 1 to m.

Abstract translation: 提供了一种字线驱动电路的扇区，包括本地复位信号发生器模块和m个字线簇。 m个字线簇耦合到本地复位信号发生器模块。 本地复位信号发生器模块用于产生j个复位信号。 根据第X预解码信号，存储体可选择信号和扇区可选择信号确定第x个复位信号，其中j是自然数，x是从1到j的整数。 每个m个字线簇包括j个行驱动器。 第y个字线簇的第x行驱动器根据第x个复位信号，第x个预解码信号确定一个[x + j *（y-1）]个字线信号， 扇区可选择信号和第y个群集选择信号，其中m是自然数，y是1至m的整数。