公开(公告)号：US12038838B2

公开(公告)日：2024-07-16

申请号：US17669649

申请日：2022-02-11

申请人： NeuroBlade Ltd.

发明人： Elad Sity ,  Eliad Hillel

IPC分类号： G06F13/36 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/14 ,  G06F13/16 ,  G06F15/78

CPC分类号： G06F12/0802 ,  G06F12/0646 ,  G06F12/1458 ,  G06F13/1657 ,  G06F13/1668 ,  G06F15/786 ,  G06F2212/1056 ,  G06F2212/60 ,  G06F2212/7202

摘要： In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.

公开(公告)号：US20240086346A1

公开(公告)日：2024-03-14

申请号：US18365793

申请日：2023-08-04

申请人： SUNRISE MEMORY CORPORATION

发明人： Weidong Zhang

IPC分类号： G06F13/16 ,  G06F13/40

CPC分类号： G06F13/1689 ,  G06F13/1657 ,  G06F13/4022

摘要： A method and system for building a block data transfer (BT) DRAM provides a solution to fix the performance gap between memory and processor. The data conversion time per word between the analog circuits and the digital circuits inside the BT DRAM is smaller than the processor clock cycle time, that enables the average data transfer speed of a BT DRAM to match to the operation speed of a processor. When continuously transferring a plurality of data blocks, a BT DRAM can achieve a close-to-zero-latency performance and is completely self-refreshing.

公开(公告)号：US11868778B2

公开(公告)日：2024-01-09

申请号：US16937189

申请日：2020-07-23

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Ganesh Dasika ,  Sergey Blagodurov ,  Seyedmohammad Seyedzadehdelcheh

IPC分类号： G06F9/34 ,  G06F9/30 ,  G06F13/16

CPC分类号： G06F9/342 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30167 ,  G06F13/1657

摘要： Compacted addressing for transaction layer packets, including: determining, for a first epoch, one or more low entropy address bits in a plurality of first transaction layer packets; removing, from one or more memory addresses of one or more second transaction layer packets, the one or more low entropy address bits; and sending the one or more second transaction layer packets.

公开(公告)号：US20190227950A1

公开(公告)日：2019-07-25

申请号：US16266526

申请日：2019-02-04

申请人： Rambus Inc.

发明人： Ian Shaeffer ,  Frederick A. Ware

IPC分类号： G06F12/14 ,  G06F12/02 ,  G06F13/16 ,  G06F3/06

CPC分类号： G06F12/1458 ,  G06F3/0619 ,  G06F12/023 ,  G06F13/16 ,  G06F13/1657 ,  G06F13/1684 ,  G06F13/1694 ,  G06F2212/1044 ,  G06F2212/1052

摘要： A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

公开(公告)号：US20190004984A1

公开(公告)日：2019-01-03

申请号：US15871637

申请日：2018-01-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： CHULSEUNG LEE ,  TAESUNG LEE ,  CHOONGEUI LEE ,  SOON SUK HWANG

IPC分类号： G06F13/16 ,  G06F13/12 ,  G06K9/62 ,  G06F15/18

CPC分类号： G06F13/1689 ,  G06F13/126 ,  G06F13/1657 ,  G06K9/6255 ,  G06N20/00

摘要： A data training method of a storage device, which includes a storage controller and a nonvolatile memory device, includes transmitting a read training command to the nonvolatile memory device, receiving a first training pattern output from the nonvolatile memory device in response to the read training command, receiving a second training pattern output from the nonvolatile memory device in response to the read training command, comparing the received first training pattern and the received second training pattern with a reference pattern, and determining a read timing offset of the storage controller depending on the comparison result.

公开(公告)号：US20180300061A1

公开(公告)日：2018-10-18

申请号：US15868535

申请日：2018-01-11

申请人： Silicon Motion, Inc.

发明人： Tzu-Wei HSU

IPC分类号： G06F3/06 ,  G06F13/16 ,  G06F13/28

CPC分类号： G06F3/0608 ,  G06F3/065 ,  G06F3/0679 ,  G06F13/1657 ,  G06F13/1678 ,  G06F13/28

摘要： A memory controller includes a central processing unit, an interface logic circuit and an arbiter circuit. The central processing unit includes an internal memory device. The interface logic circuit is coupled to an external memory device and a standard bus. The arbiter circuit is directly coupled to the central processing unit via an SRAM bus. When the central processing unit has to read predetermined data stored in the external memory device, the central processing unit issues a first request to the interface logic circuit. In response to the first request, the interface logic circuit reads the predetermined data from the external memory device and transmits the predetermined data to the arbiter circuit via the standard bus. The arbiter circuit transfers the predetermined data directly to the central processing unit via the SRAM bus to write the predetermined data in the internal memory device.

公开(公告)号：US20180253379A1

公开(公告)日：2018-09-06

申请号：US15449952

申请日：2017-03-04

申请人： International Business Machines Corporation

发明人： Alexander Cook ,  Cory J. Kleinheksel ,  David M. Koster ,  Jason A. Nikolai

IPC分类号： G06F12/0842

CPC分类号： G06F12/0842 ,  G06F13/14 ,  G06F13/161 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F2212/62

摘要： Disclosed aspects relate to cache management in a stream computing environment that uses a set of many-core hardware processors to process a stream of tuples by a plurality of processing elements which operate on the set of many-core hardware processors. The stream of tuples to be processed by the plurality of processing elements which operate on the set of many-core hardware processors may be received. A tuple-processing hardware-route on the set of many-core hardware processors may be determined based on a cache factor associated with the set of many-core hardware processors. The stream of tuples may be routed based on the tuple-processing hardware-route on the set of many-core hardware processors. The stream of tuples may be processed by the plurality of processing elements which operate on the set of many-core hardware processors.

公开(公告)号：US20180113820A1

公开(公告)日：2018-04-26

申请号：US15617117

申请日：2017-06-08

申请人： Samsung Electronics Co., Ltd.

发明人： Byung-yong KIM

IPC分类号： G06F13/16 ,  G06F13/42 ,  G06F15/78

CPC分类号： G06F13/1673 ,  G06F13/1657 ,  G06F13/4282 ,  G06F15/7821 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2213/16

摘要： Program procedures executed to rout a bus, via a processing unit, include a bus information extractor configured to extract bus information including physical requirements for the bus, from input data, a buffer array generator configured to generate a buffer array in which buffers included in the bus are regularly arranged based on the bus information, a buffer array placer configured to place at least one buffer array in the layout of the integrated circuit based on the bus information, and a wiring procedure configured to generate interconnections connected to buffers included in the at least one buffer array based on the bus information.

公开(公告)号：US09910789B2

公开(公告)日：2018-03-06

申请号：US14441857

申请日：2013-10-11

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM JAPAN, LTD.

发明人： Yasunao Katayama ,  Seiji Muneto ,  Atsuya Okazaki

IPC分类号： G06F12/00 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  H04Q11/00

CPC分类号： G06F12/14 ,  G06F13/1657 ,  G06F13/4022 ,  G06F2212/2542 ,  H04Q11/0001

摘要： A processor issues a command to a memory through an electrical memory link and performs a process according to the command through the electrical memory link. The processor issues a routing command to an optical circuit switch (OCS) through an OCS control line. In response to the routing command, the OCS establishes a routing of an optical memory link from the processor to the BDM. In response to the establishment of the optical memory link from the processor to the BDM, the processor (or a BDM (internal/dedicated) controller) switches from performing the process through the electrical memory link to performing a process through the optical memory link (continuously without an interruption between the successive processes). Corresponding systems are also disclosed herein.

公开(公告)号：US20180046375A1

公开(公告)日：2018-02-15

申请号：US15722054

申请日：2017-10-02

申请人： MICRON TECHNOLOGY, INC.

发明人： Toru Tanzawa

IPC分类号： G06F3/06 ,  G06F12/14 ,  G06F12/06 ,  G06F13/16

CPC分类号： G06F3/0604 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/06 ,  G06F12/0623 ,  G06F12/14 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1052 ,  G06F2212/214 ,  G06F2212/2532 ,  Y02D10/14

摘要： Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.